Semiconductor chip stack structure
Semiconductor chip stack structure and method are provided. A first chip has a first metal bump formed on a first electrode pad. The first chip is attached to and electrically connected to a substrate. The electrical connection is made by a bump reverse bonding method in which one end of a bonding wire is ball-bonded to the substrate and the other end is stitch-bonded to the metal bump. The second chip is stacked on the first chip. The bonding wire is substantially parallel with a top surface of the first chip. Accordingly, the chip stack structure and method minimize a space between the first chip and the second chip, thereby reducing the total height of semiconductor chip stack.
1. A semiconductor chip stack structure comprising:
a substrate including a die-mounting surface and wiring patterns adjacent the die-mounting surface;
a first semiconductor chip attached to the die-mounting surface and including first electrode pads on a top surface thereof;
first conductive bumps formed on the first electrode pads;
first bonding wires electrically interconnecting the substrate and the first conductive bumps, the first bonding wires having an expanse substantially parallel with the top surface of the first chip; and
a second semiconductor chip stacked over the first chip using the expanse of the first bonding wires, the second semiconductor chip including second electrode pads on a top surface thereof and being electrically connected to the wiring patterns, the second chip including an insulating adhesive layer on a bottom surface thereof, wherein the second chip including the insulating adhesive layer is in direct contact with the expanse,
wherein at least one of the first bonding wires contacts a portion of the insulating adhesive layer, the portion directly overlying a corresponding one of the first conductive bumps, and wherein the at least one of the first bonding wires is supported by the corresponding one of the conductive bumps.
2. The structure of claim 1 , further comprising an insulating adhesive formed between the top surface of the first chip and the second semiconductor chip, and wherein the insulating adhesive extends outwardly beyond side surfaces of the first and second chips.
3. The structure of claim 2 , wherein the insulating adhesive is epoxy or silicone insulating adhesive.
4. The structure of claim 3 , wherein the insulating adhesive hermetically seals a space between the first chip and the second chip.
5. The structure of claim 1 , wherein the insulating adhesive layer of the second chip is in contact with the first bonding wire.
6. The structure of claim 1 , wherein one end of each first bonding wire is ball-bonded to the wiring pattern of the substrate and the other end of the first bonding wire is stitch-bonded to the first metal bump of the first chip.
7. The structure of claim 1 , wherein the substrate is selected from the group consisting of a lead frame, a printed circuit board, a tape wiring substrate and a ceramic substrate.
8. The structure of claim 1 , wherein the first electrode pads are arranged along a periphery of the top surface of the first chip.
9. The structure of claim 1 , further comprising second bonding wires electrically interconnecting the second electrode pads of the second chip and the wiring patterns.
10. The structure of claim 9 , further comprising second conductive bumps formed on the second electrode pads of the second chip.
11. The structure of claim 10 , wherein one end of the second bonding wire is ball-bonded to the wiring pattern of the substrate and the other end is stitch-bonded to the second metal bump formed on the second chip.
12. The structure of claim 1 , wherein the first bonding wire has a substantially 90° bend.
13. The structure of claim 1 , wherein the adhesive layer and said expanse flushly abut one another.
14. The structure of claim 1 , wherein a bottom portion of the expanse contacts an upper portion of the corresponding one of the conductive bumps.