IP Library › Granted Patent US 6,982,612
Granted Patent B2
US 6,982,612 · App. 10/725,877 · Granted Jan 3, 2006

Duplexer and communication apparatus with a matching circuit including a trap circuit for harmonic suppression

Assignee: Murata Manufacturing Co., Ltd.
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Quick Facts
Patent No.
US 6,982,612
App. No.
10/725,877
Granted
Jan 3, 2006
Kind
B2
Abstract

A duplexer includes a transmitting filter and a receiving filter which are connected in parallel to an antenna terminal, and a matching circuit connected between the antenna terminal and at least one of the transmitting filter and the receiving filter. A portion of the matching circuit defines a trap circuit for harmonic suppression.

Claims (31)

1. A duplexer comprising:

a transmitting filter and a receiving filter which are connected in parallel to an antenna terminal; and

a matching circuit provided between the antenna terminal and at least one of the transmitting filter and the receiving filter; wherein

a portion of the matching circuit defines a trap circuit for harmonic suppression;

the trap circuit includes at least one open stub corresponding to a harmonic to be suppressed;

the matching circuit includes a parallel inductor connected between the antenna terminal and a ground; and

the parallel inductor is a wound-type chip coil.

2. A duplexer according to claim 1 , further comprising a package for housing the transmitting filter and the receiving filter, wherein the package also houses the matching circuit.

3. A duplexer according to claim 1 , wherein each of the transmitting filter and the receiving filter includes a surface acoustic wave filter.

4. A duplexer according to claim 1 , wherein the transmitting filter includes a ladder-type SAW filter having a first series SAW resonator connected to the antenna side.

5. A duplexer according to claim 4 , wherein the ladder-type SAW filter is a T-shaped ladder SAW filter.

6. A communication apparatus comprising the duplexer according to claim 1 .

7. A duplexer according to claim 1 , wherein the parallel inductor has a Q factor of at least about 20.

8. A duplexer according to claim 1 , wherein, in a passband of the transmitting filter and the receiving filter, the open stub is capacitive and the combined reactance of the open stub and the parallel inductor is capacitive.

9. A duplexer comprising:

a transmitting filter and a receiving filter which are connected in parallel to an antenna terminal; and

a matching circuit provided between the antenna terminal and at least one of the transmitting filter and the receiving filter,

at least one package for housing at least one of the transmitting filter and the receiving filter; and

a multi-layer substrate having the package and a portion of the matching circuit mounted thereon; wherein

a portion of the matching circuit defines a trap circuit for harmonic suppression;

the matching circuit includes a parallel inductor connected between the antenna terminal and a ground; and

the parallel inductor of the matching circuit includes a chip coil.

10. A duplexer according to claim 9 , wherein the trap circuit includes at least one open stub corresponding to a harmonic to be suppressed.

11. A duplexer according to claim 10 , wherein, in a passband of the transmitting filter and the receiving filter, the open stub is capacitive and the combined reactance of the open stub and the parallel inductor is capacitive.

12. A duplexer according to claim 9 , wherein the parallel inductor has a Q factor of at least about 20.

13. A duplexer according to claim 9 , wherein each of the transmitting filter and the receiving filter includes a surface acoustic wave filter.

14. A duplexer according to claim 9 , wherein the transmitting filter includes a ladder-type SAW filter having a first series SAW resonator connected to the antenna side.

15. A duplexer according to claim 14 , wherein the ladder-type SAW filter is a T-shaped ladder SAW filter.

16. A duplexer according to claim 9 , wherein the matching circuit includes a first parallel capacitor connected to the antenna terminal, a series inductor, and a second parallel capacitor, and the first parallel capacitor includes the trap circuit.

17. A communication apparatus comprising the duplexer according to claim 9 .

18. A duplexer according to claim 9 , wherein the trap circuit is provided in the multi-layer substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 2, 2003
From: SAKANO, KIWAMU
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 014755/0734 →
Priority Claims (1)
JP 2002-365968 · Dec 18, 2002 · national
Continuity (1)
Related Publication 20040119562A1 · Jun 24, 2004