Integrated circuit selective power down protocol based on acknowledgement
A system-on-chip (SOC) includes a power down circuit. Within the SOC are several circuit blocks, each of them operating responsive to a local clock signal. A system clock is coupled to the circuit blocks for providing a system clock signal that functions as the local clock signal for selected circuit blocks. A power control manager provides a signal that at least partially determines whether the system clock will act as the local clock for some of the circuit blocks. Within the circuit blocks is a shutdown circuit that selectively prevents the system clock signal from functioning as the local clock signal in those circuit blocks that receive the shutdown signal, but the shutdown circuit only operates after both the signal to shutdown is received from the power control manager and after the circuit block has, in fact, shutdown.
1. A system-on-chip (SOC) comprising:
a plurality of circuit blocks, each responsive to a respective local clock signal;
a system clock connected to said circuit blocks for providing a system clock signal thereto for functioning as the respective local clock signals;
a power control manager connected to said circuit blocks for selectively providing a shutdown signal thereto;
each circuit block comprising a shutdown circuit for preventing the system clock signal from functioning as the respective local clock signal after the circuit block receiving the shutdown signal provides a shutdown acknowledgment signal to said power control manager;
said power control manager being connected to each shutdown circuit through a respective power down request line for providing the shutdown signal thereto, and through a respective power down acknowledgment line for receiving the shutdown acknowledgment signal therefrom, said power control manager comprising
a first register connected to the respective power down request lines for storing data indicating logic states of the shutdown signals, and
a second register connected to the respective power down acknowledgment lines for storing data indicating logic states of the shutdown acknowledgment signals; and
a central processing unit connected to said power control manager for determining whether each circuit block is in an active state or an idle state by querying said first and second registers.
2. An SOC according to claim 1 , wherein each shutdown circuit comprises a clock separation circuit connected to said power control manager for preventing the system clock signal from functioning as the respective local clock signal if said corresponding circuit block receiving the shutdown signal is in an idle state.
3. An SOC according to claim 1 , wherein each circuit block further comprises a block logic circuit connected to said shutdown circuit through the respective power down request line for receiving the shutdown signal therefrom, and through the respective power down acknowledgment line for providing the shutdown acknowledgment signal thereto.
4. An SOC according to claim 1 , wherein each shutdown circuit comprises a logic circuit having a first input connected to the respective power down request line, a second input connected to the respective power down acknowledgment line, and a third input connected to said system clock, and an output for providing the respective local clock signal based upon logic states of the shutdown signal, the shutdown acknowledgment signal and the system clock signal.
5. An SOC according to claim 1 , further comprising another system clock connected to selected circuit blocks for providing a system clock signal thereto.
6. A system-on-chip (SOC) comprising:
a plurality of circuit blocks;
a system clock connected to said circuit blocks for providing a system clock signal thereto;
a power control manager connected to said circuit blocks for selectively providing a shutdown signal thereto; and
each circuit block comprising
a block logic circuit having an input for receiving the shutdown signal, and an output for providing a shutdown acknowledgment signal to said power control manager after receiving the shutdown signal, and
a shutdown circuit connected to said block logic circuit for preventing the system clock signal from functioning as a local clock signal after said block logic circuit provides the shutdown acknowledgment signal to said power control manager;
said power control manager being connected to each shutdown circuit through a respective power down request line for providing the shutdown signal thereto, and through a respective power down acknowledgment line for receiving the shutdown acknowledgment signal therefrom, said power control manager comprising
a first register connected to the respective power down request lines for storing data indicating logic states of the shutdown signals, and
a second register connected to the respective power down acknowledgment lines for storing data indicating logic states of the shutdown acknowledgment signals; and
central processing unit connected to said power control manager for determining whether each circuit block is in an active state or an idle state by querying said first and second registers.
7. An SOC according to claim 6 , wherein each shutdown circuit comprises a clock separation circuit connected to said power control manager for preventing the system clock signal from functioning as the local clock signal if said corresponding circuit block receiving the shutdown signal is in an idle state.
8. An SOC according to claim 6 , wherein each block logic circuit is connected to said shutdown circuit through the respective power down request line for receiving the shutdown signal therefrom, and through the respective power down acknowledgment line for providing the shutdown acknowledgment signal thereto.
9. An SOC according to claim 6 , wherein each shutdown circuit comprises a logic circuit having a first input connected to the respective power down request line, a second input connected to the respective power down acknowledgment line, and a third input connected to said system clock, and an output for providing the local clock signal based upon logic states of the shutdown signal, the shutdown acknowledgment signal and the system clock signal.
10. A method for powering down circuit blocks within a system-on-chip (SOC) comprising a plurality of circuit blocks, and a power control manager, the method comprising:
providing a system clock signal to the circuit blocks for functioning as a respective local clock signal;
selectively providing a shutdown signal from the power control manager to the circuit blocks;
preventing the system clock signal from functioning as the respective local clock signal after the circuit block receiving the shutdown signal provides a shutdown acknowledgment signal;
each circuit block comprising a shutdown circuit connected to the power control manager through a respective power down request line for receiving the shutdown signal therefrom, and through a respective power down acknowledgment line for providing the shutdown acknowledgment signal thereto;
the power control manager comprising a first register connected to the respective power down request lines for storing data indicating logic states of the shutdown signals, and a second register connected to the respective power down acknowledgment lines for storing data indicating logic states of the shutdown acknowledgment signals; and
determining whether each circuit block is in an active state or an idle state by querying the first and second registers.
11. A method according to claim 10 , further comprising preventing the system clock signal from functioning as the respective local clock signal if the corresponding circuit block receiving the shutdown signal is in an idle state.
12. A method according to claim 10 , wherein each circuit block further comprises a block logic circuit connected to the shutdown circuit through the respective power down request line for receiving the shutdown signal therefrom, and through the respective power down acknowledgment line for providing the shutdown acknowledgment signal thereto.
13. A method according to claim 10 , wherein each shutdown circuit comprises a logic circuit having a first input connected to the respective power down request line, a second input connected to the respective power down acknowledgment line, and a third input connected to a system clock, and an output for providing the respective local clock signal based upon logic states of the shutdown signal, the shutdown acknowledgment signal and the system clock signal.