Semiconductor device and method for manufacturing the same
A semiconductor device 100 includes wiring layers 12 disposed in a specified pattern on a base 10 , and an interlayer dielectric layer 20 that covers the wiring layers 12 . The interlayer dielectric layer 20 includes a stress relieving dielectric layer 22 disposed in a specified pattern on the base 10 , and a planarization dielectric layer 26 that covers the wiring layers 12 and the stress relieving dielectric layers 22 , and is formed from a liquid dielectric member. The interlayer dielectric layer 20 may further include a base dielectric layer 24 and a cap dielectric layer 28.
1. A semiconductor device comprising:
a base;
at least one wiring layer disposed on the base;
a stress relieving dielectric layer disposed on the base, the stress relieving dielectric layer having four contiguous strips forming a rectangular shape with each of the four strips having a constant cross-section in a direction parallel to the base;
a planarization dielectric layer disposed above the wiring layer and the stress relieving layer; and
wherein the wiring layer is separated from, and surrounded by the stress relieving dielectric layer.
2. A semiconductor device according to claim 1 , wherein the planarization dielectric layer further comprises at least one of a silicon oxide layer and another dielectric layer having a low dielectric constant.
3. A semiconductor device according to claim 1 , wherein the stress relieving dielectric layer further comprises a silicon oxide layer.
4. A semiconductor device according to claim 1 , wherein the stress relieving dielectric layer is disposed at least in a rough pattern region.
5. A semiconductor device according claim 1 , wherein the stress relieving dielectric layer has a minimum line width and a minimum gap for a wiring layer in an applied design rule.
6. A semiconductor device according to claim 1 , wherein the stress relieving dielectric layer is formed higher than the wiring layer, and an upper surface of the stress relieving dielectric layer is located higher than an upper surface of the wiring layer.
7. A semiconductor device according to claim 1 , further comprising:
a base dielectric layer formed on the wiring layer and the stress relieving dielectric layer; and
a cap dielectric layer formed on the planarization dielectric layer.