Asymmetrical programming ferroelectric memory transistor

1. A method of fabricating and programming a ferroelectric memory transistor for asymmetrical programming, comprising:

fabricating a ferroelectric memory transistor having a metal oxide layer overlaying a gate region wherein a memory window is defined by:

Δ

⁢

⁢

V

T

=

2

⁢

Q

R

C

FE

; and

programming the ferroelectric memory transistor so that a low threshold voltage is about equal to an intrinsic threshold voltage of the ferrorelectric memory transistor.

2. The method of claim 1 wherein the ferroelectric memory transistor is a MFMox transistor and the intrinsic and low threshold voltages are define by:

V

TL

=

V

FB

+

φ

SO

-

2

⁢

q

⁢

⁢

ɛ

⁢

⁢

N

A

⁢

φ

SO

-

Q

PL

C

FE

.

3. The method of claim 2 wherein Q PL is nearly equal to zero, and the ferroelectric memory transistor is a MFMox transistor and the intrinsic and low threshold voltages are define by:

V

TL

=

V

FB

+

φ

SO

-

2

⁢

q

⁢

⁢

ɛ

⁢

⁢

N

A

⁢

φ

SO

C

FE

.

4. A method of fabricating and programming a ferroelectric memory transistor for asymmetrical programming, comprising:

fabricating a ferroelectric memory transistor having a metal oxide layer overlaying a gate region wherein a memory window is defined by:

Δ

⁢

⁢

V

T

=

2

⁢

Q

R

C

FE

; and

programming the ferroelectric memory transistor so that a low threshold voltage is about equal to an intrinsic threshold voltage of the ferrorelectric memory transistor.

5. The method of claim 4 wherein the ferroelectric memory transistor is a MFMox transistor and the intrinsic and low threshold voltages are define by:

V

TL

=

V

FB

+

φ

SO

-

2

⁢

q

⁢

⁢

ɛ

⁢

⁢

N

A

⁢

φ

SO

-

Q

PL

C

FE

.

6. The method of claim 4 wherein Q PL is nearly equal to zero, and the ferroelectric memory transistor is a MFMox transistor and the intrinsic and low threshold voltages are define by:

V

TL

=

V

FB

+

φ

SO

-

2

⁢

q

⁢

⁢

ɛ

⁢

⁢

N

A

⁢

φ

SO

C

FE

.