IP Library Granted Patent US 6,995,071
Granted Patent B2
US 6,995,071 · App. 10/830,214 · Granted Feb 7, 2006

Methods of forming MIM type capacitor structures using low temperature plasma processing

Assignee: Samsung Electronics Co., Ltd.
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Quick Facts
Patent No.
US 6,995,071
App. No.
10/830,214
Granted
Feb 7, 2006
Kind
B2
Abstract

Methods of forming metal-insulator-metal type capacitors in integrated circuit memory devices can include crystallizing an HfO 2 dielectric layer on a lower electrode of a capacitor structure in a low temperature plasma treatment at a temperature in range between about 250 degrees Centigrade and about 450 degrees Centigrade. An upper electrode can be formed on the HfO 2 dielectric layer.

Claims (36)

1. A method of forming a metal-insulator-metal type capacitor structure in an integrated circuit memory device, comprising:

crystallizing an HfO 2 dielectric layer on a lower electrode of a capacitor structure in a low temperature plasma treatment at a temperature in a range between about 250 degrees Centigrade and about 450 degrees Centigrade; and

forming an upper electrode on the HfO 2 dielectric layer, wherein forming an upper electrode comprises forming the upper electrode using a metal source containing halogen or an organometallic compound, or a combination thereof.

2. A method according to claim 1 wherein crystallizing an HfO 2 dielectric layer further comprises:

crystallizing the HfO 2 dielectric layer in a range between about 350 degrees Centigrade and about 450 degrees Centigrade.

3. A method according to claim 1 wherein forming the upper electrode using a metal source further comprises forming the upper electrode using a metal source containing Cl.

4. A method according to claim 1 wherein crystallizing an HfO 2 dielectric layer further comprises:

crystallizing the HfO 2 dielectric layer in the low temperature plasma atmosphere including an N gas.

5. A method according to claim 4 wherein crystallizing an HfO 2 dielectric layer further comprises:

crystallizing the HfO 2 dielectric layer in the low temperature plasma atmosphere including NH 3 gas or N 2 O gas or N 2 gas or combinations thereof.

6. A method of forming a metal-insulator-metal type capacitor structure in an integrated circuit memory device, comprising:

forming a lower electrode on a substrate;

forming an HfO 2 dielectric layer on the lower electrode;

processing the HfO 2 dielectric layer in a plasma atmosphere at a temperature in a range between about 250 degrees Centigrade and about 450 degrees Centigrade; and

forming an upper electrode on the HfO 2 dielectric layer, wherein the upper electrode is formed using a halogen-containing metal source or an organometallic compound source or a combination thereof.

7. A method according to claim 6 wherein the lower electrode is formed of a metal nitride or a noble metal or combinations thereof.

8. A method according to claim 7 wherein the lower electrode is formed of TiN or TaN or WN or Ru or Ir or Pt or combinations thereof.

9. A method according to claim 6 wherein the HfO 2 dielectric layer is formed using atomic layer deposition or chemical vapor deposition or physical vapor deposition or metal-organic chemical vapor deposition.

10. A method according to claim 6 wherein processing the HfO 2 dielectric layer in a plasma atmosphere is performed using plasma of N-containing gas.

11. A method according to claim 10 wherein the N-containing gas includes NH 3 or N 2 O or N 2 or combinations thereof.

12. A method according to claim 6 wherein the upper electrode is formed of a metal nitride or a noble metal or combinations thereof.

13. A method according to claim 12 wherein the upper electrode is formed of TiN or TaN or WN or Ru or Ir or Pt, or combinations thereof.

14. A method according to claim 6 wherein the plasma atmosphere is maintained at a temperature in a range between about 250 degrees Centigrade and about 450 degrees Centigrade.

15. A method of forming a metal-insulator-metal type capacitor in an integrated circuit memory device, comprising:

forming a buried contact plug in a first interlayer dielectric layer on a substrate;

forming a first silicon nitride layer and a second interlayer dielectric layer on the buried contact plug;

forming a buffer buried contact plug in the first silicon nitride layer and in the second interlayer dielectric layer to contact the buried contact plug;

sequentially forming a high density plasma layer, a second silicon nitride layer, a protection layer, and an insulating layer on the buffer buried contact plug to form a cover layer;

removing a portion of the cover layer to form a hole to expose at least a portion of the buffer buried contact plug;

forming a conductive layer in the hole and outside the hole on the insulating layer using a Cl source metal;

forming a sacrificial layer on the conductive layer inside and outside the hole;

removing a portion of the sacrificial layer outside the hole to expose the insulating layer;

removing the insulating layer from around the conductive layer to form a lower electrode for the capacitor;

forming an amorphous HfO 2 dielectric layer on the lower electrode;

crystallizing the amorphous HfO 2 dielectric layer on the lower electrode in a low temperature plasma atmosphere including NH 3 gas or N 2 O gas or N 2 gas or combinations thereof in a temperature range between about 350 degrees Centigrade and about 450 degrees Centigrade to provide a crystallized HfO 2 dielectric layer; and

forming an upper electrode on the crystallized HfO 2 dielectric layer using a halogen-containing metal source or an organometallic compound source or a combination thereof.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2004
From: OH, SE-HOO; CHUNG, JUNG-HEE; CHOI, JAE HYOUNG; CHOI, JEONG SIK; KIM, SUNG-TAE; YOO, CHA YOUNG
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 015260/0946 →
Priority Claims (1)
KR 10-2003-0029368 · May 9, 2003 · national
Continuity (1)
Related Publication 20040248361A1 · Dec 9, 2004