Method for fabricating array substrate of liquid crystal display device
An array substrate of a liquid crystal display (LCD) device and a method for fabricating the same is disclosed, to decrease the unit cost and time of fabrication by decreasing the usage count of mask, which includes simultaneously forming a gate line, a gate electrode and a pixel electrode on a substrate; depositing a gate insulating layer and an active layer on an entire surface of the substrate including the gate line; patterning the gate insulating layer and the active layer to remain on the gate line and the gate electrode; selectively removing the active layer above the gate line; forming a data line perpendicular to the gate line and source/drain electrodes; and depositing a passivation layer on the entire surface of the substrate including the data line.
1. A method for fabricating an array substrate of an LCD device comprising:
simultaneously forming a gate line, a gate electrode and a pixel electrode on a substrate;
depositing a gate insulating layer and an active layer on an entire surface of the substrate including the gate line;
patterning the gate insulating layer and the active layer to remain on the gate line and the gate electrode;
selectively removing the active layer above the gate line;
forming a data line substantially perpendicular to the gate line and source/drain electrodes; and
depositing a passivation layer on the entire surface of the substrate including the data line.
2. The method of claim 1 , wherein a transparent conductive layer and a low-resistance metal layer are sequentially deposited when forming the gate line, the gate electrode and the pixel electrode.
3. The method of claim 2 , wherein the transparent conductive layer is formed of one of ITO (Indium-Tin-Oxide) and IZO (Indium-Zinc-Oxide).
4. The method of claim 2 , wherein the low-resistance metal layer is formed of one of copper Cu, aluminum Al, aluminum neodymium AlNd, molybdenum Mo, chrome Cr, titanium Ti, tantalum Ta and molybdenum-tungsten MoW.
5. The method of claim 2 , further comprising removing the low-resistance metal layer of the pixel electrode after patterning the gate insulating layer and the active layer.
6. The method of claim 1 , wherein the active layer above the gate line is completely removed when selectively removing the active layer above the gate line.
7. The method of claim 1 , wherein the active layer above the gate line is partially removed when selectively removing the active layer above the gate line.
8. The method of claim 1 , wherein forming the data line includes forming a storage upper electrode overlapping the adjacent gate line and electrically connected with the pixel electrode.
9. The method of claim 1 , wherein a pad electrode extends from the gate line and another pad electrode extends from the data line.
10. The method of claim 1 , wherein patterning the gate insulating layer and the active layer includes:
depositing a photoresist on the gate insulating layer and the active layer;
patterning the photoresist to remain on the gate line and the gate electrode by diffraction exposure; and
etching the gate insulating layer and the active layer by using the patterned photoresist as a mask.
11. The method of claim 10 , wherein the photoresist patterned by the diffraction exposure is thinner than rest of the photo resist.
12. The method of claim 11 , wherein selectively patterning the active layer above the gate line includes:
removing the thin portion of the photoresist by ashing; and
selectively removing a portion of the active layer by using the ashed photoresist as a mask.
13. The method of claim 10 , wherein one of a half-tone mask and a slit mask is used for the diffraction exposure process.
14. A method for fabricating an array substrate of an LCD device comprising:
depositing a conductive layer on a substrate, and simultaneously forming a gate line, a gate electrode and a pixel electrode by photolithography using a first mask;
forming a gate insulating layer, a semiconductor layer and a photoresist on an entire surface of the substrate including the gate line, and patterning the gate insulating layer and the semiconductor layer to remain on the gate electrode and the gate line by patterning the photoresist with a diffraction exposure process using a second mask;
selectively removing the semiconductor layer above the gate line after ashing the photoresist; and
depositing a metal layer on the entire surface of the substrate including the semiconductor layer, and forming a data line and source/drain electrodes using a third mask.
15. The method of claim 14 , wherein a transparent conductive layer and a low-resistance metal layer are sequentially deposited in the step of forming the gate line, the gate electrode and the pixel electrode.
16. The method of claim 15 , further comprising removing the low-resistance metal layer of the pixel electrode when patterning the gate insulating layer and the semiconductor layer.
17. The method of claim 15 , wherein the transparent conductive layer is formed of one of ITO (Indium-In-Oxide) and IZO (Indium-Zinc-Oxide).
18. The method of claim 15 , wherein the low-resistance metal layer is formed of one of copper Cu, aluminum Al, aluminum neodymium AlNd, molybdenum Mo, chrome Cr, titanium Ti, tantalum Ta and molybdenum-tungsten MoW.
19. The method of claim 14 , wherein the semiconductor layer above the gate line is completely removed when selectively removing the semiconductor layer above the gate line.
20. The method of claim 14 , wherein the semiconductor layer above the gate line is partially removed when selectively removing the semiconductor layer above the gate line.
21. The method of claim 14 , wherein the second mask is formed of one of a half-tone mask and a slit mask.