Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS using altering process
The present invention pertains to an automated method for designing a integrated circuit (IC) design-specific cell, the method includes the steps of receiving a design specification for the design-specific cell, mapping a transistor-level representation of the design-specific cell, wherein the mapping is based on at least one, but perhaps plural design specifications, and evaluating the transistor-level representation of the design-specific cell for satisfaction of the design specification.
1. An automated method for designing an integrated circuit (IC) design-specific cell, said method comprising the steps of:
receiving a design specification for electrical behavior or transistor-level characteristics of said design-specific cell;
mapping said design specification to a transistor-level representation of said design-specific cell;
evaluating said transistor-level representation of said design-specific cell for meeting said design specification; and
altering said transistor-level representation of said design-specific cell to meet said design specification.
2. The method of claim 1 , wherein said step of evaluating comprises evaluating said transistor-level representation of said design-specific cell based on a specific design context in which said design-specific cell is to be used.
3. The method of claim 1 , wherein said step of receiving comprises receiving a description of said design-specific cell.
4. The method of claim 3 , wherein said description is selected from a group consisting of a netlist representation, a descriptive language representation, and a standard-cell representation of said design-specific cell, wherein said standard-cell is used in an IC design process.
5. The method of claim 1 , wherein said design specification is selected from the group consisting of: size (area), signal timing, transistor sizing, number of transistors, power consumption, length of interconnects within said design-specific cell, output signal strength, input signal impedance, noise characteristics, and a combination thereof.
6. The method of claim 1 , wherein said step of mapping comprises:
generating a transistor netlist based on at least one netlist generation algorithm; and
evaluating said generated transistor netlist based on at least one design specification.
7. The method of claim 6 , wherein said step of mapping further comprises optimizing transistor size for said generated transistor netlist.
8. The method of claim 1 , wherein said step of mapping is based on at least one of a plurality of topology formats.
9. The method of claim 1 , wherein said method further comprises the step of creating at least one transistor-level redundancy for aiding in satisfying said design specification.
10. The method of claim 1 , wherein said method further comprises the step of detecting an implementation weakness in a cell for implementing said IC.
11. The method of claim 1 , wherein said design specification comprises electrical behavior and transistor-level characteristics of said design-specific cell.
12. The method of claim 1 , wherein said integrated circuit design-specific cell is selected from the group consisting of: CMOS cells, static CMOS cells, dynamic CMOS cells and combinations thereof.
13. A system for automatically designing an integrated circuit (IC) design-specific cell, said system comprising:
an interface for receiving a design specification for electrical behavior or transistor-level characteristics of said design-specific cell;
a mapping process that maps said design specification to a transistor-level representation of said design-specific cell;
an evaluating process that evaluates said transistor-level representation of said design-specific cell for determining whether said transistor-level representation of said IC meets said design specification; and
an alteration process that alters said transistor-level representation of said design-specific cell to meet said design specification.
14. The system of claim 13 , wherein said evaluating process evaluates said transistor-level representation of said design-specific cell based on a specific design context in which said design-specific cell is to be used.
15. The system of claim 13 , wherein said interface receives a description of said design-specific cell.
16. The system of claim 15 , wherein said description received by said interface is selected from a group consisting of: a netlist representation, a descriptive language representation, and a standard-cell representation of said design-specific cell, wherein said standard-cell is used in an IC design process.
17. The system of claim 13 , wherein said mapping process controls the mapping of said transistor-level representation on the basis of said design specification selected from the group consisting of: size (area), signal timing, transistor sizing, number of transistors, power consumption, fault tolerance, integrity characteristics, noise characteristics, and a combination thereof.
18. The system of claim 13 , wherein said mapping process generates a transistor netlist based on at least one netlist generation algorithm; and evaluates said generated transistor netlist based on at least one design specification.
19. The system of claim 13 , wherein said mapping process further comprises a controller that controls the mapping using a plurality of topology formats.
20. The system of claim 13 , wherein said mapping process further comprises a controller for optimization of transistor sizing for said generated transistor netlist.
21. The system of claim 13 , wherein said system further comprises a process that creates at least one transistor-level redundancy for said IC cell for aiding in meeting said design specification.
22. The system of claim 13 , wherein said system further comprises a detector that detects an implementation weakness in a cell for implementing said IC.
23. The system of claim 13 , wherein said design specification comprises electrical behavior and transistor-level characteristics of said design-specific cell.
24. The system of claim 13 , wherein said integrated circuit design-specific cell is selected from the group consisting of: CMOS cells, static CMOS cells, dynamic CMOS cells and combinations thereof.
25. A design-specific cell produced by an automated integrated circuit (IC) design process, said IC design process comprises the steps of:
receiving a design specification for electrical behavior or transistor-level characteristics of said design-specific cell;
mapping said design specification to a transistor-level representation of said design-specific cell,
evaluating said transistor-level representation of said design-specific cell for meeting of said design specification; and
altering said transistor-level representation of said design-specific cell to meet said design specification.
26. The design-specific cell produced by the IC design process of claim 25 , wherein said step of evaluating comprises evaluating said transistor-level representation of said design-specific cell based on a specific design context in which said design-specific cell is to be used.
27. The design-specific cell produced by the IC design process of claim 25 , wherein said step of receiving comprises receiving a description of said design-specific cell.
28. The design-specific cell produced by the IC design process of claim 27 , wherein said description is selected from a group consisting of: a netlist representation, a descriptive language representation, and a standard-cell representation of said design-specific cell, wherein said standard-cell is used in an IC design process.
29. The design-specific cell produced by the IC design process of claim 25 , wherein said design specification is selected from the group consisting of: size (area), signal timing, transistor sizing, number of transistors, power consumption, length of interconnects within said design-specific cell, output signal strength, input signal impedance, noise characteristics, and a combination thereof.
30. The design-specific cell produced by the IC design process of claim 25 , wherein said step of mapping comprises:
generating a transistor netlist based on at least one netlist generation algorithm; and
evaluating said generated transistor netlist based on at least one design specification.
31. The design-specific cell produced by the IC design process of claim 30 , wherein said step of mapping further comprises optimizing the transistor size for said generated transistor netlist.
32. The design-specific cell produced by the IC design process of claim 25 , wherein said step of mapping is based on at least one plurality of topology format.
33. The design-specific cell produced by the IC design process of claim 25 , wherein said method further comprises the step of creating at least one transistor-level redundancy for aiding in meeting said design specification.
34. The design-specific cell produced by an automated integrated circuit (IC) design process of claim 25 , wherein said design specification comprises electrical behavior and transistor-level characteristics of said design-specific cell.
35. The design-specific cell of claim 25 , wherein the integrated circuit design-specific cell is selected from the group consisting of: CMOS cells, static CMOS cells, dynamic CMOS cells and combinations thereof.
36. A storage medium having computer readable program instructions embodied therein for automatically designing an integrated circuit (IC) design-specific cell, said storage medium comprising:
program instructions for receiving a design specification for electrical behavior or transistor-level characteristics of said design-specific cell;
program instructions for mapping said design specification to a transistor-level representation of said design-specific cell;
program instructions for evaluating said transistor-level representation of said design-specific cell for satisfaction of said design specification; and
program instructions for altering said transistor-level representation of said design-specific cell to meet said design specification.
37. The storage medium of claim 36 , wherein said design specification comprises electrical behavior and transistor-level characteristics of said design-specific cell.
38. The storage medium of claim 36 , wherein said integrated circuit design-specific cell is selected from the group consisting of: CMOS cells, static CMOS cells, dynamic CMOS cells and combinations thereof.