IP Library Granted Patent US 7,005,733
Granted Patent B2
US 7,005,733 · App. 09/745,811 · Granted Feb 28, 2006

Anti tamper encapsulation for an integrated circuit

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Quick Facts
Patent No.
US 7,005,733
App. No.
09/745,811
Granted
Feb 28, 2006
Kind
B2
Abstract

An integrated circuit device comprising: a circuit which uses encryption; and an encapsulation packaging layer; in which the circuit is responsive to at least one physical parameter of the encapsulation to apply the encryption and/or decryption by reading the key therefrom, so that tampering with the encapsulation to gain access to the circuit causes the encryption and/or decryption to fail.

Claims (46)

1. An integrated circuit device comprising:

a protective member which reduces access to the device;

one or more sensors for sensing one or more physical parameters from the protective member; and

a circuit which encrypts and decrypts protected data,

wherein the circuit is adapted to derive encryption values from the one or more physical parameters sensed, the encryption values being essential to the process of encrypting and decrypting the protected data, such that tampering with the protective member to gain access to the circuit corrupts the encryption values.

2. A device according to claim 1 , in which the circuit comprises a memory in which protected data is stored in encrypted form.

3. A device according to claim 1 , in which the circuit comprises bus lines for connection to a separate memory device.

4. A device according to claim 2 or 3 , in which said memory is read-only, and said circuit comprises a decryptor arranged to apply a decryption algorithm to data read therefrom.

5. A device according to claim 2 or 3 , in which said memory is writeable, and said circuit comprises an encryptor arranged to apply an encryption algorithm to data to be protected to be written thereto.

6. A device according to claim 2 or 3 , in which said memory comprises at least a first memory and a second memory, and said first memory stores data encryption to be used to decrypt data stored in said second memory, and said circuit is responsive to the parameter to decrypt the contents of the first memory.

7. A device according to claim 1 , in which the protective member comprises an encapsulation around the circuit.

8. A device according to claim 1 , in which the circuit comprises an encryptor arranged to apply an encryption and/or decryption algorithm to data to be protected or said protected data.

9. A device according to claim 1 , wherein said protective member includes at least one decrystallised portion of a crystalline solid.

10. A device according to claim 1 , further comprising tamper-detection logic, responsive to an attempt to gain access to the circuit to generate a tamper signal.

11. A device according to claim 1 , in which the circuit is jointly responsive both to said physical parameter and to predetermined secret encryption data to apply the encryption and/or decryption.

12. A device according to claim 11 , further comprising tamper-detection logic, responsive to attempt to gain access to the circuit to generate a tamper signal.

13. A device according to claim 12 , in which the circuit is arranged to erase the predetermined secret encryption data in response to the tamper signal.

14. A device according to claim 1 , further comprising a shield surrounding the protective member, and arranged to reduce the effects of external conditions on the physical parameter.

15. A device according to claim 1 , further comprising at least one sensor responsive to said protective member, from which said at least one parameter can be derived by said circuit.

16. A device according to claim 15 , further comprising a plurality of sensors to sense said at least one physical parameter.

17. A device according to claim 16 , in which said sensors are disposed in an array over at least part of said circuit.

18. A device according to claim 17 , in which the inter-sensor spacing is on the order of a micron.

19. A device according to claim 16 , farther comprising a scanning circuit arranged to periodically read said sensors.

20. A device according to claim 19 , in which said scanning circuit is arranged to vary the order of reading said sensors.

21. A device according to claim 19 , further comprising a checking circuit arranged to check whether the outputs of said sensors correspond to previous values thereof.

22. The device according to claim 1 , wherein said altering of the encryption and/or decryption process occurs regardless of a power state of said device.

23. The device according to claim 1 , wherein the tampering alters one or more one or more physical parameters, resulting in the inability to derive said encryption values used to decrypt said protected data.

24. An integrated circuit device comprising:

a protective member which reduces access to the device;

one or more sensors for sensing one or more physical parameters from the protective member; and

a circuit which encrypts and decrypts protected data,

wherein the circuit is adapted to derive encryption values from the one or more physical parameters sensed, the encryption values being essential to the process of encrypting and decrypting the protected data, such that tampering with the protective member to gain access to the circuit corrupts the encryption values,

in which the circuit comprises an encryptor arranged to apply an encryption and/or decryption algorithm to data to be protected or said protected data and

in which said encryptor is arranged to use an encryption key, and to the circuit is arranged to derive said key from said parameters.

25. A device according to claim 1 , in which said parameter is an electrical parameter.

26. A device according to claim 1 , in which said parameter is a magnetic parameter.

27. A device according to claim 1 , in which said parameter is an optical parameter.

28. A device according to claim 1 , in which said parameter is a radiation parameter.

29. A device according to claim 1 , wherein said protective member includes a plurality of particles to which said circuit is responsive, within a matrix material.

30. A device according to claim 29 , wherein said particles are metallic.

31. A device according to claim 29 , wherein said particles are radioactive.

32. A device according to claim 29 , wherein said matrix allows passage of radiation, and said parameter is an optical property affected by said particles.

33. A device according to claim 32 , in which said particles are radiation-producing.

34. A device according to claim 32 , in which said particles are radiation-absorbing.

35. A device according to claim 32 , in which said particles are radiation-scattering.

36. An integrated circuit device comprising a memory in which data is stored in encrypted form, and a circuit for encrypting and/or decrypting to write and/or read the data, the circuit comprising a key register storing a key for use in said encryption and/or decryption process, and an alternation circuit arranged to vary the data stored in the key register at frequent intervals.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2019
From: AMERICAN IMAGING CARTRIDGE, LLC
To: UNIVERSAL IMAGING INDUSTRIES, LLC
Reel/Frame 047944/0777 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2014
From: KÖMMERLING, FRITZ
To: AMERICAN IMAGING CARTRIDGE, LLC
Reel/Frame 034569/0287 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2014
From: KÖMMERLING, OLIVER
To: AMERICAN IMAGING CARTRIDGE, LLC
Reel/Frame 034167/0865 →
Continuity (2)
Provisional Application 6017399400 · Dec 30, 1999
Related Publication 20010033012A1 · Oct 25, 2001