IP Library Granted Patent US 7,009,590
Granted Patent B2
US 7,009,590 · App. 10/137,602 · Granted Mar 7, 2006

Display apparatus and display method

Assignee: Sharp Kabushiki Kaisha
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,009,590
App. No.
10/137,602
Granted
Mar 7, 2006
Kind
B2
Abstract

A display apparatus conducting time-division gradation display is provided with: a capacitor for keeping a signal level captured by a first TFT; at least one pixel memory, for keeping the signal level captured by the first TFT; a second TFT matched with the corresponding pixel memory; and a bit selecting line for selectively-driving the second TFT, wherein, when a scanning signal line is selected, the first TFT sets the display signal level is set in the capacitor via the first TFT and the second TFT is selectively driven so that the display signal level is set in the at least one pixel memory, whereas the TFT is selectively driven so that a display signal level which has been displayed is switched to the display signal level supplied from the at least one pixel memory.

Claims (53)

1. A display apparatus, comprising:

electro-optical devices in respective areas partitioned by a plurality of first signal lines and a plurality of second signal lines intersecting with each other, each of the electro-optical devices being driven so as to carry out displaying in accordance with a signal level supplied via the second signal line while a first active device being selected via the corresponding first signal line;

at least one second active device corresponding to the electro-optical device;

at least one pixel memory, corresponding to the at least one second active device, for storing a signal level captured by the at least one second active device;

electric potential keeping means for keeping a signal level captured by the first active device; and

at least one bit selecting line for selectively driving the at least one second active device,

wherein, while the first signal line is selected and a display signal level is set in the electric potential keeping means through the first active device, the at least one second active device is selectively driven so that the display signal level is also set in the at least one pixel memory, and the at least one second active device is selectively driven when the first signal lines is not selected, so that a display signal level of the electric potential keeping means is switched to the display signal level in the at least one pixel memory, and

when time-division gradation display is carried out using an active organic EL, a bit appearing more than once in one frame is kept in an SRAM, while a bit appearing only once in one frame is kept in a capacitor, and

when display period of weight is less than scanning time, the gap is filled as a data display period of the pixel memory, and time-division gradation driving is carried out.

2. The display apparatus as defined in claim 1 , further comprising third active devices each provided to each of the electric potential keeping means, for supplying a signal level, which is different from the signal level supplied to the second signal line, to the electric potential keeping means, in response to a selective-output supplied from a third signal line which supplies an output while the first signal lines does not supply an output, wherein the first active device sets the display signal level, meanwhile the third active device sets an erase signal level.

3. The display apparatus as defined in claim 1 , wherein the electric potential keeping means is constituted by a fourth active device and a capacitor.

4. The display apparatus as defined in claim 1 , wherein a fifth active device is provided between an input of the at least one pixel memory and an output of the at least one pixel memory, and while the fifth active device is subjected to non-selective driving, the display signal level of the at least one pixel memory is set.

5. The display apparatus as defined in claim 1 , wherein the at least one pixel memory receives power from a second power supply line which is independent from a first power supply line that provides a load current to the electro-optical device.

6. A display apparatus, including device circuits provided in a matrix manner, comprising:

first signal lines each provided to a different row of the device circuits;

bit selecting lines each provided to a different row of the device circuits; and

second signal lines each provided to a different column of the device circuits,

wherein, each of the device circuits further includes:

a first active device which is selected via the corresponding first signal line so as to capture a signal supplied to the corresponding second signal line;

a pixel memory including a second active device which is selected via the corresponding bit selecting line, the pixel memory either (i) keeping the signal captured by the first signal line when the first signal line is selected, or (ii) outputting the signal which has been kept therein when the first signal line is not selected, in response. to the selection of the second signal line;

signal keeping means which keeps either (i) the signal captured by the first active device instead of a signal which has been kept therein or (ii) the signal which is output from the pixel memory instead of a signal which has been kept therein; and

an electro-optical device for emitting light in accordance with the signal kept in the signal keeping means, and carrying out time-division gradation display using an active organic EL, and

when display period of weight is less than scanning time, the gap is filled as a data display period of the pixel memory, and time-division gradation driving is carried out.

7. The display apparatus as defined in claim 6 , wherein a plurality of the bit selecting lines is provided to a different row of the device circuits, and each of the device circuits includes a plurality of the pixel memories corresponding to the plurality of the bit selecting lines, and carrying out time-division gradation display using an active organic EL.

8. The display apparatus as defined in claim 6 , further comprising third signal lines each provided to a different row of the device circuits, wherein, each of the device circuits further includes a third active device for erasing the signal kept in the signal keeping means in response to selection via the corresponding third signal line and when time-division gradation display is carried out using an active organic EL, a bit appearing more than once in one frame is kept in an SRAM, while a bit appearing only once in one frame is kept in a capacitor.

9. The display apparatus as defined in claim 8 , further comprising:

first power supply lines each provided to a different column of the device circuits; and

second power supply lines each provided to a different column of the device circuits,

wherein, in each of the device circuits, the electro-optical device is driven by a current supplied through the corresponding first power supply line, and the pixel memory and the signal keeping means are driven by a voltage supplied through the corresponding second power supply line.

10. The display apparatus as defined in claim 6 , further comprising:

first power supply lines each provided to a different column of the device circuits; and

second power supply lines each provided to a different column of the device circuits,

wherein, in each of the device circuits, the electro-optical device is driven by a current supplied through the corresponding first power supply line, and the pixel memory and the signal keeping means are driven by a voltage supplied through the corresponding second power supply line.

11. The display apparatus as defined in claim 6 , wherein the pixel memory includes a static memory to which an input of an inverter circuit and an output of another inverter circuit are connected, and the pixel memory keeps a signal on account of the static memory.

12. The display apparatus as defined in claim 6 , wherein the pixel memory includes a capacitor, and the pixel memory keeps a signal on account of the capacitor, and carrying out time-division gradation display using an active organic EL.

13. The display apparatus as defined in claim 6 , further comprising selecting lines each provided to a different row of the device circuits, wherein the signal keeping means is provided with (i) a capacitor for keeping a signal and (ii) a fourth active device, which is situated between the capacitor and the pixel memory, for bringing the capacitor and the pixel memory into conduction when selected via the corresponding selecting line.

14. A display method of a display apparatus including electro-optical devices in respective areas partitioned by a plurality of first signal lines and a plurality of second signal lines intersecting with each other, each of the electro-optical devices carrying out displaying in accordance with a signal level supplied via the corresponding second signal line while a first active device being selected via the corresponding first signal line, comprising the steps of:

setting a display signal level in an electric potential keeping means via the first active device while the first signal line is selected, and selectively driving the second active device so that the display signal level is set in the pixel memory; and

switching a display signal level of the electro-optical device to the display signal level set in the pixel memory, by selectively-driving the second active device while the first signal line is not selected; and

when time-division gradation display is carried out using an active organic EL, a bit appearing more than once in one frame is kept in an SRAM, while a bit appearing only once in one frame is kept in a capacitor, and

when display period of weight is less than scanning time, the gap is filled as a data display period of the pixel memory, and time-division gradation driving is carried out.

15. A display method of a display apparatus provided with:

device circuits provided in a matrix manner; first signal lines each provided to a different row of the device circuits;

bit selecting lines each provided to a different row of the device circuits; and

second signal lines each provided to a different column of the device circuits,

each of the device circuits including:

a first active device which captures a display signal supplied via the corresponding second signal line, in response to selection of the first active device by the corresponding first signal line;

a pixel memory including a second active device which is selected by the corresponding bit selecting line, the pixel memory either (i) keeping the signal captured by the first signal line when the first signal line is selected, or (ii) outputting the signal which has been kept therein when the first signal line is not selected, in response to the selection of the second active device;

signal keeping means which keeps either (i) the signal captured by the first active device or (ii) the signal which is output from the pixel memory; and

an electro-optical device for emitting light in accordance with the signal kept in the signal keeping means, comprising the steps of:

setting a display signal level in the signal keeping means via the first active device while the first signal line is selected, and selecting the bit selecting line so as to set a display signal in the pixel memory via the first and second active devices; and

selecting the bit selecting line while the first signal line is not selected, and switching a display signal of the signal keeping means to the display signal set in the pixel memory, and

carrying out time-division gradation display using an active organic EL, wherein when display period of weight is less than scanning time, the gap is filled as a data display period of the pixel memory, and time-division gradation driving is carried out.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2002
From: NUMAO, TAKAJI
To: SHARP KABUSHIKI KAISHA
Reel/Frame 012869/0822 →
Priority Claims (3)
JP 2001-145504 · May 15, 2001 · national
JP 2001-343711 · Nov 8, 2001 · national
JP 2002-081833 · Mar 22, 2002 · national
Continuity (1)
Related Publication 20030011314A1 · Jan 16, 2003