TFT array substrate and active-matrix addressing liquid-crystal display device

1. A TFT array substrate comprising:

(a) a transparent plate;

(b) TFTs arranged on the plate in a matrix array with rows and columns,

each of the TFTs having a first source/drain region, a second source/drain region, and an active layer;

(c) gate lines formed on the plate in such a way as to extend along the rows of the matrix;

(d) data lines formed on the plate in such a way as to extend along the columns of the matrix,

each of the data lines being electrically connected to corresponding ones of the TFTs at their first source/drain regions;

(e) pixel electrodes formed in pixel areas on the plate,

each of the pixel electrodes being electrically connected to corresponding ones of the TFTs at their second source/drain regions;

(f) a patterned first light-shielding layer formed between the plate and the TFTs in such a way as to overlap with the active layers of the TFTs;

(g) a patterned second light-shielding layer formed between the first light-shielding layer and the TFTs,

the second light-shielding layer having a light-absorbing property; and

(h) a patterned third light-shielding layer formed to cover the TFTs on an opposite side to the plate with respect to the TFTs,

the third light-shielding layer having first parts extending along the rows of the matrix and second parts extending along the columns thereof.

2. The substrate according to claim 1 , wherein each of the TFTs has a channel region and a LDD region;

the second light-shielding layer having first parts covering the channel regions of the TFTs and second parts covering the LDD regions thereof.

3. The substrate according to claim 1 , wherein the second light-shielding layer is made of a material including silicon.

4. The substrate according to claim 1 , wherein the second light-shielding layer has conductivity;

the second light-shielding layer having a structure that allows application of a constant voltage.

5. The substrate according to claim 1 , wherein the second light-shielding layer has conductivity and/is connected electrically to the gate lines.

6. The substrate according to claim 1 , wherein the second light-shielding layer is made of silicon doped with an impurity.

7. The substrate according to claim 1 , wherein the gate lines are arranged in such a way as to overlap with the channel regions of the corresponding TFTs;

and wherein the gate lines have a function of gate electrodes of the TFTs at their overlapping parts.

8. The substrate according to claim 1 , further comprising gate electrodes formed for the respective TFTs separately from the gate lines;

wherein the gate lines are electrically connected to the corresponding gate electrodes.

9. The substrate according to claim 1 , wherein a dielectric sandwiched by the second light-shielding layer and the active layers of the TFTs has a thickness ranging from 100 nm to 500 nm.

10. The substrate according to claim 1 , wherein a dielectric sandwiched by the second light-shielding layer and the active layers of the TFTs has a thickness ranging from 150 nm to 300 nm.

11. The substrate according to claim 1 , wherein a driver circuit section including TFTs is provided in addition to a pixel matrix section where the TFTs are arranged in a matrix array;

and wherein the second light-shielding layer is provided for the TFTs in the pixel matrix section while the second light-shielding layer is not provided for the TFTs in the driver circuit section.

12. An active-matrix addressing LCD device comprising:

(a) a TFT array substrate according to claim 1 ;

(b) an opposite substrate located to be opposite to the TFT array substrate; and

(c) a liquid-crystal layer formed between the TFT array substrate and the opposite substrate.

13. A TFT array substrate comprising:

(a) a transparent plate;

(b) TFTs arranged on the plate in a matrix array with rows and columns,

each of the TFTs having a first source/drain region, a second source/drain region, and an active layer;

(c) gate lines formed on the plate in such a way as to extend along the rows of the matrix;

(d) data lines formed on the plate in such a way as to extend along the columns of the matrix,

each of the data lines being electrically connected to corresponding ones of the TFTs at their first source/drain regions;

(e) pixel electrodes formed in pixel areas on the plate,

each of the pixel electrodes being electrically connected to corresponding ones of the TFTs at their second source/drain regions;

(f) a patterned first light-shielding layer formed between the plate and the TFTs in such a way as to overlap with the active layers of the TFTs;

(g) a patterned third light-shielding layer formed to cover the TFTs on an opposite side to the plate with respect to the TFTs,

the third light-shielding layer having first parts extending along the rows of the matrix and second parts extending along the columns thereof; and

(h) a patterned fourth light-shielding layer formed between the TFTs and the third light-shielding layer,

the fourth light-shielding layer having a light-absorbing property.

14. The substrate according to claim 13 , wherein each of the TFTs has a channel region and a LDD region;

and wherein the fourth light-shielding layer has first parts covering the channel regions of the TFTs and second parts covering the LDD regions thereof.

15. The substrate according to claim 13 , wherein the fourth light-shielding layer is made of a material including silicon.

16. The substrate according to claim 13 , wherein the fourth light-shielding layer has conductivity; the fourth light-shielding layer having a structure that allows application of a constant voltage.

17. The substrate according to claim 13 , wherein the fourth light-shielding layer has conductivity and is connected electrically to the gate lines.

18. The substrate according to claim 13 , wherein the fourth light-shielding layer is made of silicon doped with an impurity.

19. The substrate according to claim 13 , wherein the gate lines are arranged in such a way as to overlap with the channel regions of the corresponding TFTs;

and wherein the gate lines have a function of gate electrodes of the TFTs at their overlapping parts.

20. The substrate according to claim 13 , wherein gate electrodes are formed for the respective TFTs separately from the gate lines;

and wherein the gate lines are electrically connected to the corresponding gate electrodes.

21. The substrate according to claim 13 , further comprising a patterned second light-shielding layer formed between the first light-shielding layer and the TFTs;

wherein the second light-shielding layer has a light-absorbing property.

22. The substrate according to claim 21 , wherein a dielectric sandwiched by the second light-shielding layer and the active layers of the TFTs has a thickness ranging from 100 nm to 500 nm.

23. The substrate according to claim 21 , wherein a dielectric sandwiched by the second light-shielding layer and the active layers of the TFTs has a thickness ranging from 150 nm to 300 nm.

24. The substrate according to claim 21 , wherein a driver circuit section including TFTs is provided in addition to a pixel matrix section where the TFTs are arranged in a matrix array;

and wherein the second light-shielding layer is provided for the TFTs in the pixel matrix section while the second light-shielding layer is not provided for the TFTs in the driver circuit section.

25. An active-matrix addressing LCD device comprising:

(a) a TFT array substrate according to claim 13 ;

(b) an opposite substrate located to be opposite to the TFT array substrate; and

(c) a liquid-crystal layer formed between the TFT array substrate and the opposite substrate.