Method of fabricating robust nucleation/seed layers for subsequent deposition/fill of metallization layers
A method for fabricating a seed layer. A seed layer ( 126 ) is deposited over a barrier layer ( 124 ) using a three-step process comprising a low AC bias power step, a high AC bias power step, and a lower/zero AC bias power step. The low AC bias power step provides low overhang. The high AC bias power step provides good sidewall coverage. The lower/zero AC bias step recovers areas exposed by re-sputtering during the high AC bias power step.
1. A method of fabricating an integrated circuit, comprising the steps of:
depositing material to form a layer using a low AC bias power;
depositing additional material to said layer using a high AC bias power; and
depositing additional material to said layer using a lower AC bias power, wherein said high AC bias power is higher than both said low AC bias power and said lower AC bias power.
2. The method of claim 1 , wherein said material comprises copper.
3. The method of claim 1 , wherein said material comprises a copper alloy.
4. The method of claim 1 , wherein said low AC bias power is in the range of 0 W to 600 W.
5. The method of claim 1 , wherein said low AC bias power is in the range of 0 W to 400 W.
6. The method of claim 1 , wherein said high AC bias power is in the range of 300 W to 1200 W.
7. The method of claim 1 , wherein said high AC bias power is in the range of 600 W to 1000 W.
8. The method of claim 1 , wherein said lower AC bias power is in the range of 0 W to 300 W.
9. The method of claim 1 , wherein said lower AC bias power is 0 W.
10. The method of claim 1 , wherein said step of depositing with said low AC bias power occurs prior to said step of depositing with said high AC bias power.
11. The method of claim 1 , wherein said step of depositing with said low AC bias power occurs after said step of depositing with said high AC bias power.
12. A method of fabricating an integrated circuit comprising the steps of:
forming a dielectric layer over a semiconductor body;
forming a hole in said dielectric layer;
depositing a barrier layer over said dielectric layer including in said hole;
depositing a seed layer over said barrier layer using a three-step process comprising a low AC bias power step, a high AC bias power step, and a lower AC bias power step, wherein said high AC bias power step is higher than both said low AC bias power step and said lower AC bias power step; and
filling said hole with a metal using an electrochemical deposition process.
13. The method of claim 12 , wherein said seed layer comprises copper.
14. The method of claim 12 , wherein said seed layer comprises a copper alloy.
15. The method of claim 12 , wherein said low AC bias power is in the range of 0 W to 400 W.
16. The method of claim 12 , wherein said high AC bias power is in the range of 600 W to 1000 W.
17. The method of claim 12 , wherein said lower AC bias power is 0 W.
18. The method of claim 12 , wherein said low AC bias power step occurs prior to said high AC bias power step.
19. The method of claim 12 , wherein said low AC bias power step occurs after said high AC bias power step.
20. A method of fabricating an integrated circuit comprising the steps of:
forming a dielectric layer over a semiconductor body;
forming a via in said dielectric layer;
forming a trench in said dielectric layer;
depositing a barrier layer over said dielectric layer including in said trench and said via;
depositing a first portion of a seed layer over said barrier layer using a low AC bias power;
depositing a second portion of said seed layer using a high AC bias power;
depositing a third portion of said seed layer using a lower AC bias power, wherein said high AC bias power is higher than both said low AC bias power and said lower AC bias power; and
filling said hole with a metal using an electrochemical deposition process.
21. The method of claim 20 , wherein said seed layer comprises copper.
22. The method of claim 20 , wherein said seed layer comprises a copper alloy.
23. The method of claim 20 , wherein said low AC bias power is in the range of 0 W to 400 W.
24. The method of claim 20 , wherein said high AC bias power is in the range of 600 W to 1000 W.
25. The method of claim 20 , wherein said lower AC bias power is 0 W.
26. The method of claim 20 , wherein said seed layer has a final thickness and said first portion is 20% to 70% of said final thickness.
27. The method of claim 20 , wherein said seed layer has a final thickness and said first portion is 50% to 60% of said final thickness.
28. The method of claim 20 , wherein said seed layer has a final thickness and said second portion is 20% to 70% of said final thickness.
29. The method of claim 20 , wherein said seed layer has a final thickness and said second portion is 30% to 40% of said final thickness.
30. The method of claim 20 , wherein said seed layer has a final thickness and said first portion is 1% to 30% of said final thickness.
31. The method of claim 20 , wherein said seed layer has a final thickness and said first portion is 10% to 20% of said final thickness.