Methods for making a dielectric stack in an integrated circuit
An ultrathin aluminum oxide and lanthanide layers, particularly formed by an atomic layer deposition (ALD) type process, serve as interface layers between two or more materials. The interface layers can prevent oxidation of a substrate and can prevent diffusion of molecules between the materials. In the illustrated embodiments, a high-k dielectric material is sandwiched between two layers of aluminum oxide or lanthanide oxide in the formation of a transistor gate dielectric or a memory cell dielectric. Aluminum oxides can serve as a nucleation layer with less than a full monolayer of aluminum oxide. One monolayer or greater can also serve as a diffusion barrier, protecting the substrate from oxidation and the high-k dielectric from impurity diffusion. Nanolaminates can be formed with multiple alternating interface layers and high-k layers, where intermediate interface layers can break up the crystal structure of the high-k materials and lower leakage levels.
1. An integrated circuit comprising an interface layer between a conductive material and a dielectric material, the interface layer comprising a lanthanide oxide and having a thickness less than or equal to about 4 molecular monolayers, wherein the dielectric material is characterized by a dielectric constant greater than about 10.
2. The integrated circuit of claim 1 , further comprising a second interface layer directly contacting an opposite side of the dielectric material, and a second conductive material directly over the second interface layer, the second interface layer selected from the group consisting of aluminum oxide and lanthanide oxides and having a thickness of less than or equal to about 4 molecular monolayers.
3. The integrated circuit of claim 2 , wherein the conductive material comprises a silicon substrate, wherein the second conductive material comprises a gate electrode, and wherein the interface layer, dielectric material and second interface layer form a gate dielectric for an integrated transistor.
4. The integrated circuit of claim 2 , wherein the conductive material comprises a storage electrode in a memory cell, and the second conductive material comprises a reference electrode, wherein the interface layer, dielectric material and second interface layer form a capacitor dielectric for an integrated capacitor.
5. The integrated circuit of claim 1 , wherein the interface layer has a thickness between about 3 Å and 15 Å.
6. The integrated circuit of claim 5 , wherein the interface layer has a thickness between about 3 Å and 9 Å.
7. An integrated circuit comprising a plurality of alternating interface and dielectric layers between a conductive material and a dielectric material, each interface layer having a thickness between about 1 Å and 15 Å, each dielectric layer having a dielectric constant of greater than about 5, and at least one interface layer comprising a lanthanide oxide.
8. The integrated circuit of claim 7 , wherein at least one interface layer comprises aluminum oxide and each dielectric layer comprises zirconium oxide.