IP Library › Granted Patent US 7,038,292
Granted Patent B2
US 7,038,292 · App. 10/711,036 · Granted May 2, 2006

Substrate isolation design

Assignee: United Microelectronics Corp.
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Quick Facts
Patent No.
US 7,038,292
App. No.
10/711,036
Granted
May 2, 2006
Kind
B2
Abstract

A substrate isolation design includes a P substrate, a P well positioned on the P substrate, at least a device positioned in the P well, and at least a P substrate guard ring surrounding the device. A P+ guard ring, an N well guard ring, or a deep N well guard ring can be selectively interposed between the P substrate guard ring and the device to facilitate blocking substrate coupling effect.

Claims (33)

1. A substrate isolation design, comprising:

a P substrate;

a P well positioned on the substrate;

at least a device positioned in the P well;

at least a P substrate guard ring surrounding the device; and

an N well guard ring positioned between the device and the P substrate guard ring,

wherein the P substrate guard ring is positioned beneath a shallow isolation trench formed within the P well.

2. The substrate isolation design of claim 1 , further comprising at least a P+ guard ring surrounding the device.

3. The substrate isolation design of claim 2 , wherein the P+ guard ring is between the device and the P substrate guard ring.

4. The substrate isolation design of claim 3 , wherein the N well guard ring is positioned between the P+ guard ring and the P substrate guard ring.

5. The substrate isolation design of claim 4 , further comprising at least a deep N well guard ring positioned beneath the P well to contact to the N well guard ring.

6. The substrate isolation design of claim 1 , wherein the N well guard ring surrounds the device.

7. The substrate isolation design of claim 6 , wherein the N well guard ring is between the device and the P substrate guard ring.

8. The substrate isolation design of claim 7 , further comprising at least a deep N well guard ring positioned beneath the P well to contact to the N well guard ring.

9. A substrate isolation design, comprising:

a substrate;

at least a device positioned on the substrate;

a first guard ring surrounding the device;

a second guard ring surrounding the first guard ring; and

a third guard ring surrounding the second guard ring, the third guard ring being a substrate guard ring, wherein the second guard ring comprises an N well guard ring and the substrate guard ring is positioned beneath a shallow isolation trench.

10. The substrate isolation design of claim 9 , wherein the first guard ring comprises a P+ guard ring.

11. The substrate isolation design of claim 9 , wherein the third guard ring comprises a P substrate guard ring.

12. The substrate isolation design of claim 9 , further comprising at least a deep N well guard ring connecting to the N well guard ring.

13. A substrate isolation design, comprising:

a P substrate;

at least a device positioned in the substrate;

at least a P substrate guard ring surrounding the device; and

an N well guard ring positioned between the device and the P substrate guard ring,

wherein the P substrate guard ring is positioned beneath a shallow isolation trench.

14. The substrate isolation design of claim 13 , further comprising at least a P+ guard ring positioned between the device and the P substrate guard ring.

15. The substrate isolation design of claim 14 , wherein the N well guard ring is between the P+ guard ring and the P substrate guard ring.

16. The substrate isolation design of claim 15 , further comprising at least a deep N well guard ring contacting to the N well guard ring.

17. The substrate isolation design of claim 13 , further comprising at least a deep N well guard ring contacting to the N well guard ring.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2004
From: HSU, TSUN-LAI
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 015003/0496 →
Continuity (1)
Related Publication 20060038271A1 · Feb 23, 2006