Air gap interconnect structure and method of manufacture
View Patent ↗A dual layer of polymeric material is deposited with a base layer and top layer resist onto an integrated circuit structure with topography. The base layer planarizes the surface and fills in the native topography. The base layer decomposes almost completely when exposed to an oxidizing environment. The top layer contains a high composition of oxidizing elements and is photosensitive. (i.e., the layer can be patterned by exposing normal lithographic techniques.) The patterning allows the creation of escape paths for the decomposition products of the underlying base layer. This structure is decomposed in an oxidizing ambient (or plasma) leaving behind a thin carbon-containing membrane. This membrane layer blocks deposition of future layers, creating air gaps in the structure.
1. A method of forming air gaps in a starting structure on a semiconductor substrate comprising:
depositing a first layer comprising a first material on the starting structure;
depositing a second layer comprising a second material on the first layer;
patterning the second layer, resulting in gaps between portions of the second layer; and
subjecting the substrate to a highly oxidizing environment so that the first material will substantially completely decompose into volatile products and the second material will partially decompose leaving a thin membrane layer.
2. A method, according to claim 1 , wherein:
the first layer is deposited by a spin-on process.
3. A method, according to claim 1 , wherein:
the second layer is deposited by a spin-on process.
4. A method, according to claim 1 , wherein:
the first material comprises comprises a polymer based material which is easily decomposed at low temperatures or in an oxygen plasma.
5. A method, according to claim 1 , wherein:
the second material comprises comprises a polymer based material which is easily decomposed at low temperatures or in an oxygen plasma, and has a high content of an oxidizable component.
6. A method, according to claim 1 , wherein:
the second material comprises a resist containing a high composition of silicon (Si), or aluminum (Al) or any metal which forms a strong coherent oxide film upon oxidation.
7. A method, according to claim 1 , wherein:
the thin membrane comprises an oxide containing a significant amount of carbon.
8. A method, according to claim 1 , wherein:
the second material is photosensitive, and is patterned using photolithography.
9. A method, according to claim 1 , wherein:
the starting structure is a wiring layer comprising conductive lines.
10. A method, according to claim 9 , wherein:
when the second layer is patterned, selected portions of the second layer are disposed over selected adjacent ones of the conductive lines of the starting structure.
11. A method, according to claim 9 , wherein:
air gaps between adjacent conductive lines are sealed off by portions of the thin membrane layer.
12. A method, according to claim 9 , wherein:
the conductive lines are disposed atop an underlying layer; and
there are gaps between adjacent conductive lines; and
the first material fills the gaps and covers the conductive lines.
13. A method, according to claim 12 , wherein:
when the second layer is patterned, selected ones of the gaps of the second layer are disposed over selected ones of gaps between adjacent ones of the conductive lines of the starting structure.
14. A method, according to claim 9 , wherein:
the conductive lines are disposed within a dielectric layer;
there are troughs between adjacent conductive lines; and
the first material fills the troughs and covers the conductive lines.
15. A method, according to claim 14 , wherein:
when the second layer is patterned, selected ones of the gaps of the second layer are disposed over selected ones of the troughs between adjacent ones of the conductive lines of the starting structure.
16. A method, according to claim 1 , further comprising:
depositing an interlevel dielectric (ILD) on the surface of the substrate.