Semiconductor memory device
A column switch in a two-port SRAM (static random access memory) is provided with A-port switches, B-port switches, and inter-port switches. When it is detected that an A-port row address and a B-port row address match each other, all of the B-port switches are turned off, and an A-port bit line pair for a column selected according to A-port column decode signals is coupled to an A-port data line pair, while an A-port bit line pair for a column selected according to B-port column decode signals is coupled to a B-port data line pair.
1. A semiconductor memory device comprising:
a memory cell array in which a plurality of memory cells are arranged two-dimensionally in a plurality of rows and a plurality of columns, each of the memory cells having first- and second-port word lines and first- and second-port bit line pairs;
a first row decoder for driving the first-port word line of memory cells in a row selected from the plurality of rows in the memory cell array according to a first-port row address;
a second row decoder for driving the second-port word line of memory cells in a row selected from the plurality of rows in the memory cell array according to a second-port row address;
a row address comparison circuit for detecting whether or not the first-port row address and the second-port row address match each other and controlling the first and second row decoders in such a manner that when it is detected that the first-port and second-port row addresses do not match each other, the first and second row decoders are both operated, and when it is detected that the first-port and second-port row addresses match each other, only the first row decoder is operated; and
a column switch interposed between a set of the first-port bit line pairs and the second-port bit line pairs, each of which is shared by memory cells in a corresponding one of the columns in the memory cell array, and a set of a first-port data line pair and a second-port data line pair, each of which is shared by the columns in the memory cell array,
wherein when the row address comparison circuit detects that the first-port row address and the second-port row address do not match each other, the column switch connects, to the first-port data line pair, the first-port bit line pair of memory cells in a column selected from the plurality of columns in the memory cell array according to the first-port column address, and connects, to the second-port data line pair, the second-port bit line pair of memory cells in a column selected from the plurality of columns in the memory cell array according to the second-port column address, and
when the row address comparison circuit detects that the first-port row address and the second-port row address match each other, the column switch connects, to the first-port data line pair, the first-port bit line pair of the memory cells in the column selected from the plurality of columns in the memory cell array according to the first-port column address, and connects, to the second-port data line pair, the first-port bit line pair of the memory cells in the column selected from the plurality of columns in the memory cell array according to the second-port column address.
2. The device of claim 1 , wherein upon detecting that the first-port row address and the second-port row address match each other, the row address comparison circuit stops supply of a word line clock signal to the second row decoder, thereby halting operation of the second row decoder.
3. The device of claim 1 , wherein the column switch includes:
a set of first-port switches each interposed between a corresponding one of the first-port bit line pairs, which is shared by the memory cells in the corresponding column in the memory cell array, and the first-port data line pair;
a set of second port switches each interposed between a corresponding one of the second-port bit line pairs, which is shared by the memory cells in the corresponding column in the memory cell array, and the second-port data line pair; and
a set of inter-port switches each interposed between a corresponding one of the first-port bit line pairs, which is shared by the memory cells in the corresponding column in the memory cell array, and the second-port data line pair.