Backgated FinFET having different oxide thicknesses
View Patent ↗A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.
1. A method of fabricating a FinFET semiconductor structure, comprising steps of:
forming a fin for a FinFET on a substrate, the fin having first and second sides;
introducing a first impurity on the first side of the fin; and
forming a dielectric layer on the first and second sides, wherein the dielectric layer is thicker on one of the first and second sides than the other of the first and second sides, and the introduced impurity affects dielectric layer thickness.
2. The method according to claim 1 , wherein the first impurity is a substance that retards dielectric layer formation.
3. The method according to claim 2 , wherein the first impurity includes one of nitrogen, nitrogen ions or nitrogen containing compounds.
4. The method according to claim 1 , wherein the first impurity is a substance that enhances dielectric layer formation.
5. The method according to claim 4 , wherein the first impurity includes one of silicon, argon, cesium, oxygen or germanium, or ions or compounds thereof.
6. The method according to claim 1 , wherein the step of introducing a first impurity is comprised of a step of directional implantation.
7. The method according to claim 6 , wherein the step of directional implantation includes tilting the structure to a predetermined angle of incidence with the impurity being implanted.
8. The method according to claim 1 , wherein the substrate is comprised of a buried oxide layer.
9. The method according to claim 1 , further including a step of introducing a second impurity on the second side of the fin.
10. The method according to claim 9 , wherein the first impurity is a substance that retards dielectric layer formation and the second impurity is a substance that enhances dielectric formation.
11. The method according to claim 10 , wherein:
the first impurity includes one of nitrogen, nitrogen ions or nitrogen containing compounds; and
the second impurity includes one of silicon, argon, cesium, oxygen or germanium, or ions or compounds thereof.
12. The method according to claim 10 , wherein:
the step of introducing a first impurity is comprised of a step of directional implantation directed to the first side of the fin; and
the step of introducing a second impurity is comprised of a step of directional implantation directed to the second side of the fin.
13. The method according to claim 12 , wherein the steps of directional implantation include tilting the structure to a predetermined angle of incidence with the impurity being implanted.
14. A method of fabricating a FinFET semiconductor structure, comprising steps of:
forming a fin for a FinFET on a substrate, the fin having first and second sides;
directionally implanting a first impurity on the first side of the fin;
forming a dielectric layer on the first and second sides, the dielectric layer being thicker on one of the first and second sides than the other of the first and second sides, due to the introduced impurity affecting dielectric layer thickness; and
forming a FinFET gate straddling the fin, the FinFET gate having front and back gate sides and a top surface.
15. The method according to claim 14 , further comprising a step of backgating the back gate side of the gate.
16. The method according to claim 15 , wherein the step of backgating the back gate side of the gate includes applying a bias to the back gate side of the gate.
17. The method according to claim 14 , further comprising a step of doping the gate regions on the structure.
18. The method according to claim 17 , wherein an n-type impurity is implanted directionally on one side of the gate and a p-type impurity is implanted directionally on the other side of the gate.
19. The method according to claim 14 , further comprising a step of forming source and drain regions on the structure.
20. The method according to claim 19 , wherein the step of forming source and drain regions on the structure further includes:
directionally implanting a source dopant into the source region; and
directionally implanting a drain dopant into the drain region.
21. The method according to claim 19 , further comprising a step of forming spacers abutting the FinFET gate.
22. The method according to claim 21 , further comprising a step of planarizing the top surface of the gate.