Prediction of issued silent store operations for allowing subsequently issued loads to bypass unexecuted silent stores and confirming the bypass upon execution of the stores

1. An apparatus comprising:

a predictor having a collision history table (CHT), said predictor for predicting silent store instructions;

a processing section coupled to the predictor, the processing section including

an extended load buffer coupled to the predictor;

a marking processing section;

a comparing processing section; and

a recovery processing section, wherein unexecuted load instructions are advanced over associated silent store instructions without flushing the load instructions,

wherein the predictor compares an unexecuted load instruction value with an issued and unexecuted store instruction value, and the unexecuted load instruction bypasses the issued store instruction for execution if the unexecuted load instruction value and the issued and unexecuted store value are the same, and the unexecuted load instruction is dependent on the issued and unexecuted store instruction.

2. The apparatus of claim 1 , wherein the predictor is a silent store predictor.

3. The apparatus of claim 2 , wherein the silent store predictor uses path based indexing and the path is based on branches.

4. The apparatus of claim 3 , wherein the silent store predictor is coupled with a state machine.

5. The apparatus of claim 4 , wherein the state machine is one of a 1-bit, a 2-bit and a sticky bit.

6. The apparatus of claim 1 , wherein the predictor is memory dependent.

7. The apparatus of claim 1 , wherein the extended load buffer comprises bit fields to mark load address match, load data match, load predict, and load flush, and bit fields for load address, load attribute and load data.

8. The apparatus of claim 1 , wherein the CHT is one of indexed by a tag and tagless.

9. The apparatus of claim 1 , wherein the CHT includes distance bits.

10. A system comprising:

a processor having internal memory,

a bus coupled to the processor;

a memory coupled to a memory controller and the processor;

wherein the processor includes:

a predictor having a collision history table (CHT), said predictor for predicting silent store instructions;

an extended load buffer coupled to the predictor;

a marking process;

a comparing process; and

a recovery process,

wherein unexecuted load instructions are advanced over associated store instructions without flushing the load instructions, and the predictor compares an unexecuted load instruction value with an issued and unexecuted store instruction value, and the unexecuted load instruction bypasses the issued store instruction for execution if the unexecuted load instruction value and the issued and unexecuted store value are the same, and the unexecuted load instruction is dependent on the issued and unexecuted store instruction.

11. The system of claim 10 , wherein the predictor is a silent store predictor.

12. The system of claim 11 , wherein the silent store predictor uses path based indexing and the path is based on branches.

13. The system of claim 12 , wherein the silent store predictor is coupled with a state machine.

14. The system of claim 13 , wherein the state machine is one of a 1-bit, a 2-bit and a sticky bit.

15. The system of claim 10 , wherein the predictor is memory dependent.

16. The system of claim 10 , wherein the extended load buffer comprises

bit fields to mark load address match, load data match, load predict, and load flush, and bit fields for load address, load attribute and load data.

17. The system of claim 10 , wherein the CHT is one of indexed by a tag and tagless.

18. The system of claim 10 , wherein the CHT includes distance bits.

19. A method comprising:

fetching an instruction and determining if an instruction is one of a store and a load;

performing a silent store prediction if the instruction is a store; issuing the store instruction;

comparing an address and data of the store instruction with load instructions in an extended load buffer;

setting marking bits in the extended load buffer if a match is found in the comparing;

updating a memory with the store instruction if the store instruction can be retired; and

bypassing a predicted silent store instruction if an associated unexecuted load instruction value matches the issued and unexecuted store instruction value and executing the load instruction ahead of the predicted silent store instruction without flushing load instructions, wherein the unexecuted load instruction is dependent on the issued and unexecuted store instruction.

20. The method of claim 19 , further comprising preparing the executed load instruction for retirement if the load instruction is complete, and determining if the load instruction is marked flush in the extended load buffer.

21. The method of claim 19 , wherein the predicting includes marking bits in a collision history table (CHT).

22. The method of claim 19 , wherein the memory is a cache.

23. A program storage device readable by a machine comprising instructions that cause the machine to:

fetch an operation and determining if the operation is one of a store instruction and a load instruction;

perform a silent store prediction if the operation is a store instruction;

execute the store operation;

compare an address and data of the store operation with load operations in an extended load buffer;

set marking bits in the extended load buffer if a match is found in the compare instruction;

update a memory with a store operation if the store operation can be retired; and

bypass a predicted silent store operation and execute an associated load operation ahead of the silent store operation without flushing load instructions if the operation is a load and the load operation includes a value that matches a value included in the store operation, wherein the load operation is unexecuted and is dependent on the silent store operation.

24. The program storage device of claim 23 , wherein the instructions further cause the machine to prepare the load operation for retirement if the load operation is complete, and determining if the load operation is marked flush in the extended load buffer.

25. The program storage device of claim 23 , wherein the instruction that causes the machine to predict silent stores includes an instruction that causes the machine to mark bits in a collision history table (CHT).

26. The program storage device of claim 23 , wherein the memory is a cache.