Method of forming damascene pattern in a semiconductor device
The present invention relates to a method of forming damascene pattern in a semiconductor device, and the method includes forming an insulating layer on a bottom wiring, forming via holes exposing a part of the bottom wiring by removing the insulating layer selectively, filling insides of the via holes to a prescribed thickness, forming an anti-reflection layer on the via holes and the insulating layer, forming a mask pattern for trench etching on the insulating layer on which the anti-reflection layer is formed, and forming a damascene pattern using the mask pattern for trench etching. CD uniformity is improved by minimizing change of the critical dimension of the damascene pattern, thereby increasing reliability of the semiconductor device.
1. A method of forming damascene pattern in a semiconductor device, the method comprising:
forming an insulating layer on a bottom wiring;
forming via holes that expose a part of the bottom wiring by removing the insulating layer selectively;
filling insides of the via holes to a prescribed thickness using non-conductive material by forming a non-conductive material layer on the insulating layer in which the via holes are formed and selectively removing the non-conductive material layer to expose the insulating layer and allow the non-conductive material to remain for a prescribed thickness;
forming an anti-reflection layer on the via holes and the insulating layer;
forming a mask pattern for trench etching in the insulating layer on which the anti-reflection layer is formed; and
forming a damascene pattern after forming trenches using the mask pattern.
2. The method of claim 1 , wherein the non-conductive material layer is made of photoresist.
3. The method of claim 1 , wherein said selective removal utilizes entire surface dry etching process or chemical mechanical polishing process.