Methods of fabricating semiconductor device having T-shaped gate and L-shaped spacer
There are provided methods of fabricating a semiconductor device having a T-shaped gate and an L-shaped spacer. In the method, an insulating layer and a sacrificial layer are formed in sequence on a semiconductor substrate having a vertical gate pattern. By etching the sacrificial layer, a sacrificial spacer is formed. By etching the insulating layer until an upper surface of at least the vertical gate pattern is exposed, there is formed an L-shaped spacer, which includes a vertical portion located between sidewalls of the vertical gate pattern and the sacrificial spacer, and a horizontal portion extended from the vertical portion and located between the semiconductor substrate and the sacrificial spacer. By selectively etching a part of the vertical portion of the L-shaped spacer, an empty space is formed between upper sidewalls of the vertical gate pattern and the sacrificial spacer. A horizontal gate pattern, which is formed of a conductive layer to fill at least the empty space, is formed, and thus, there is formed a T-shaped gate being composed of the vertical gate pattern and the horizontal gate pattern.
1. A method of fabricating a semiconductor device comprising:
forming a vertical gate pattern on a semiconductor substrate;
sequentially forming an insulating layer and a sacrificial layer on the semiconductor substrate having the vertical gate pattern, the sacrificial layer being formed of a material having an etch selectivity with respect to the insulating layer;
etching the sacrificial layer to form a sacrificial spacer;
etching the insulating layer until at least an upper surface of the vertical gate pattern is exposed, to form an L-shaped spacer, the L-shaped spacer including a vertical portion located between sidewalls of the vertical gate pattern and the sacrificial spacer, and a horizontal portion extended from the vertical portion and located between the semiconductor substrate and the sacrificial spacer;
selectively etching a part of the vertical portion of the L-shaped spacer, to form an empty space between upper sidewalls of the vertical gate pattern and the sacrificial spacer;
forming a horizontal gate pattern formed of a conductive layer to fill at least the empty space, to provide a T-shaped gate composed of the vertical gate pattern and the horizontal gate pattern; and
removing the sacrificial spacer.
2. The method according to claim 1 , further comprising, after removing the sacrificial spacer, reducing a thickness of the horizontal portion of the L-shaped spacer.
3. The method according to claim 1 , wherein forming the horizontal gate pattern comprises forming a conductive layer on an upper surface and upper sidewalls of the vertical gate pattern by a selective growth method.
4. The method according to claim 3 , wherein forming the horizontal gate pattern comprises forming a first epitaxial layer on an upper surface and upper sidewalls of the vertical gate pattern.
5. The method according to claim 4 , wherein while the horizontal gate pattern is formed, a second epitaxial layer is formed on the semiconductor substrate at both ends of the sacrificial spacer.
6. The method according to claim 5 , further comprising, after forming the first epitaxial layer and the second epitaxial layer, performing an ion implantation to form high concentration source/drain regions using the T-shaped gate and the sacrificial spacer as ion implantation masks.
7. The method according to claim 6 , further comprising, after removing the sacrificial spacer, performing an ion implantation using the T-shaped gate and the L-shaped spacer as ion implantation masks, to form low concentration source/drain regions inside the semiconductor substrate, overlapping the horizontal portion of the L-shaped spacer.
8. The method according to claim 7 , further comprising, after removing the sacrificial spacer, reducing a thickness of the horizontal portion of the L-shaped spacer.
9. The method according to claim 5 , wherein the vertical gate pattern, the first epitaxial layer and the second epitaxial layer are formed of a material containing silicon.
10. The method according to claim 9 , further comprising:
forming a metal layer on the semiconductor substrate having the first epitaxial layer and the second epitaxial layer;
performing a thermal treatment to react the first epitaxial layer and the second epitaxial layer with the metal layer, to form silicide layers on the T-shaped gate pattern and the semiconductor substrate; and
removing the metal layer remaining after the silicide layers are formed.
11. The method according to claim 1 , wherein forming the horizontal gate pattern comprises:
forming a conductive layer on the semiconductor substrate having the empty space; and
patterning the conductive layer.
12. The method according to claim 11 , wherein the conductive layer is formed of a polysilicon layer.
13. The method according to claim 11 , further comprising, after forming the horizontal gate pattern, performing an ion implantation using the T-shaped gate and the sacrificial spacer as ion implantation masks, to form high concentration source/drain regions.
14. The method according to claim 13 , further comprising, after removing the sacrificial spacer, performing an ion implantation using the T-shaped gate and the L-shaped spacer as ion implantation masks, to form low concentration source/drain regions.
15. The method according to claim 12 , further comprising, after removing the sacrificial spacer, reducing a thickness of the horizontal portion of the L-shaped spacer.
16. The method according to claim 1 , further comprising, after sequentially forming the insulating layer and the sacrificial layer:
overall-etching the sacrificial layer until an upper surface of the insulating layer is exposed, to form the sacrificial spacer; and
etching the insulating layer exposed after the sacrificial spacer is formed, to form the L-shaped spacer and the empty space at the same time.
17. A method of fabricating a semiconductor device comprising:
forming a vertical gate pattern on a semiconductor substrate;
forming an insulating layer spacer on sidewalls of the vertical gate pattern;
sequentially forming an insulating layer and a sacrificial layer on the semiconductor substrate having the insulating layer spacer, the sacrificial layer being formed of a material having an etch selectivity with respect to the insulating layer;
etching the sacrificial layer to form a sacrificial spacer;
etching the insulating layer until at least an upper surface of the vertical gate pattern is exposed, to form an L-shaped spacer, the L-shaped spacer including a vertical portion located between the insulating layer spacer and the sacrificial spacer, and a horizontal portion extended from the vertical portion and located between the semiconductor substrate and the sacrificial spacer;
selectively etching parts of the vertical portion of the L-shaped spacer and the insulating layer spacer, to form an empty space between upper sidewalls of the vertical gate pattern and the sacrificial spacer;
forming a horizontal gate pattern formed of a conductive layer to fill at least the empty space, to provide a T-shaped gate being composed of the vertical gate pattern and the horizontal gate pattern; and
removing the sacrificial spacer.
18. The method according to claim 17 , wherein forming the horizontal gate pattern comprises forming a conductive layer on an upper surface and upper sidewalls of the vertical gate pattern by a selective growth method.
19. The method according to claim 18 , wherein forming the horizontal gate pattern comprises forming a first epitaxial layer on an upper surface and upper sidewalls of the vertical gate pattern.
20. The method according to claim 19 , wherein while the horizontal gate pattern is formed, a second epitaxial layer is formed on the semiconductor substrate at both ends of the sacrificial spacer.
21. The method according to claim 20 , further comprising, after forming the first epitaxial layer and the second epitaxial layer, performing an ion implantation to form high concentration source/drain regions using the T-shaped gate and the sacrificial spacer as ion implantation masks.
22. The method according to claim 21 , further comprising, after removing the sacrificial spacer, performing an ion implantation using the T-shaped gate and the L-shaped spacer as ion implantation masks, in order to form low concentration source/drain regions inside the semiconductor substrate, overlapping the horizontal portion of the L-shaped spacer.
23. The method according to claim 22 , further comprising, after removing the sacrificial spacer, reducing a thickness of the horizontal portion of the-L-shaped spacer.
24. The method according to claim 20 , wherein the vertical gate pattern, the first epitaxial layer and the second epitaxial layer are formed of a material containing silicon.
25. The method according to claim 24 , further comprising:
forming a metal layer on the semiconductor substrate having the first epitaxial layer and the second epitaxial layer;
performing a thermal treatment to react the first epitaxial layer and the second epitaxial layer with the metal layer, to form silicide layers on the T-shaped gate pattern and the semiconductor substrate; and
removing the metal layer remaining after the silicide layers are formed.
26. The method according to claim 17 , wherein forming the horizontal gate pattern comprises:
forming a conductive layer on the semiconductor substrate having the empty space; and
patterning the conductive layer.
27. The method according to claim 26 , wherein the conductive layer is formed of a polysilicon layer.
28. The method according to claim 25 , further comprising, after forming the horizontal gate pattern, performing an ion implantation using the T-shaped gate and the sacrificial spacer as ion implantation masks, to form high concentration source/drain regions.
29. The method according to claim 28 , further comprising, after removing the sacrificial spacer, performing an ion implantation using the T-shaped gate and the L-shaped spacer as ion implantation masks, to form low concentration source/drain regions.
30. The method according to claim 29 , further comprising, after removing the sacrificial spacer, reducing a thickness of the horizontal portion of the L-shaped spacer.