Multiply-accumulate (MAC) unit for single-instruction/multiple-data (SIMD) instructions
A tightly coupled dual 16-bit multiply-accumulate (MAC) unit for performing single-instruction/multiple-data (SIMD) operations may forward an intermediate result to another operation in a pipeline to resolve an accumulating dependency penalty. The MAC unit may also be used to perform 32-bit×32-bit operations.
1. An article comprising a machine-readable medium which stores machine-executable instructions, the instructions causing a machine to:
perform a first compression operation in a first multiply-accumulate operation in a pipeline;
generate two or more intermediate vectors in a first compression operation in the first multiply-accumulate operation; and
forward at least a portion of each of the two or more intermediate vectors to a second multiply-accumulate operation in the pipeline prior to completion of the first multiply-accumulate operation.
2. The article of claim 1 , wherein the instructions causing the machine to forward at least a portion of each of the two or more intermediate vectors include instructions causing the machine to forward a lower number of bits of each of the two or more intermediate vectors.
3. The article of claim 1 , wherein the instructions causing the machine to perform the first compression operation include instructions causing the machine to compress a first plurality of partial products into a first sum vector and a first carry vector and compress a second plurality of partial products into a second sum vector and a second carry vector.
4. The article of claim 1 , wherein the instructions causing the machine to generate two or more intermediate vectors include instructions causing the machine to compress the first and second sum vectors and the first and second carry vectors into an intermediate sum vector and an intermediate carry vector.
5. The article of claim 1 , wherein the instructions causing the machine to forward include instructions causing the machine to forward at least a portion of each of the two or more intermediate vectors to a Wallace tree compression unit.
6. An article comprising a machine-readable medium which stores machine-executable instructions, the instructions causing a machine to:
compress a first plurality of partial products into a first sum vector and a first carry vector and compressing a second plurality of partial products into a second sum vector and a second carry vector in a first Wallace tree compression stage of a first multiply-accumulate operation;
compress the first and second sum vectors and the first and second carry vectors into a first intermediate sum vector and a first intermediate carry vector;
compress the intermediate sum vector and a third plurality of partial products and compressing the intermediate carry vector and a fourth plurality of partial products in a second stage of the first multiply-accumulate operation; and
forward the intermediate sum and carry vectors to a second multiply-accumulate operation in a pipeline prior to completion of the first multiply-accumulate operation.
7. The article of claim 6 , wherein the first multiply-accumulate operation comprises a single instruction/multiple data (SIMD) operation.
8. The article of claim 6 , further comprising instructions causing the machine to:
generate the first plurality of partial products from a first pair of operands;
generate the second plurality of partial products from a second pair of operands;
generate the third plurality of partial products from a third pair of operands; and
generate the fourth plurality of partial products from a fourth pair of operands.
9. The article of claim 6 , wherein the instructions causing the machine to forward include instructions causing the machine to eliminate an accumulate data dependency in the second multiply-accumulate operation.