Semiconductor device with resistor pattern and method of fabricating the same
Disclosed is a semiconductor device with a resistor pattern and methods of fabricating the same. Embodiments of the present invention provide a method of fabricating a resistor pattern having high sheet resistance by using a polycide layer for a gate electrode in a semiconductor device with the resistor pattern. Embodiments of the invention also provide a semiconductor device with a resistor pattern that is formed narrower than the minimum line width that can be defined in a photolithographic process so that sheet resistance thereof increases, and a method of fabricating the same.
1. A semiconductor device comprising:
a device isolation layer disposed in a substrate to define an active region;
source and drain regions formed in the active region;
a gate electrode formed on the active region between the source and drain regions;
a gate insulation layer interposed between the gate electrode and the active region;
a resistor pattern formed on the device isolation layer;
resistor spacers disposed on sidewalls of the resistor pattern;
an interlayer dielectric layer disposed over the resistor pattern; and
resistor electrodes connected to both ends of the resistor pattern, respectively, wherein the gate electrode includes a polysilicon layer and a silicide layer that are sequentially stacked on the gate insulation layer, wherein the resistor pattern includes a single-layer polysilicon layer, wherein substantially the entire resistor pattern does not have a silicide layer disposed thereon, wherein the resistor spacer protrudes above the resistor pattern, and wherein the interlayer dielectric layer contacts a portion of the resistor spacer.
2. The device of claim 1 , wherein the gate insulation layer is multi-layered and includes at least one charge storage dielectric layer.
3. The device of claim 1 , wherein the resistor pattern is in direct contact with the device isolation layer.
4. The device of claim 1 , wherein the resistor pattern includes the polysilicon layer with a hollow region where the device isolation layer is exposed and a region adjacent the hollow region is a single polysilicon layer.
5. The device of claim 4 , further comprising:
upper spacers formed on the polysilicon layer and including a vertical sidewall an a curved sidewall; and
resistor spacers formed on outer sidewalls of the polysilicon layer an vertical sidewalls of the upper spacers, wherein the curved sidewall of he upper spacer is aligned to inner sidewalls of the polisilicon layer and the verical sidewall thereof, opposite to the curved sidewall, is aligned to an outer sidwall of the polysilicon layer.
6. The device of claim 1 , wherein the gate insulation layer is multi-layered and includes at least one charge storage dielectric layer.
7. The device of claim 6 , wherein the charge storage dielectric layer comprises silicon nitride.
8. The device of claim 2 , wherein the charge storage dielectric layer comprises silicon nitride.
9. A semiconductor device comprising:
a device isolation layer disposed in a substrate to define an active region;
source and drain regions formed in the active region;
a gate electrode formed on the active region between the source and drain regions;
a gate insulation layer interposed between the gate electrode and the active region;
a resistor pattern formed on the device isolation layer;
resistor insulating spacers disposed on sidewalls of the resistor pattern, each resistor insulating spacer having a vertical inner sidewall;
an interlayer dielectric layer disposed over the resistor pattern; and
resistor electrodes connected to both ends of the resistor pattern, respectively, wherein the gate electrode includes a polysilicon layer and a silicide layer that are sequentially stacked on the gate insulation layer, wherein the resistor pattern includes a single-layer polysilicon layer, wherein substantially the entire resistor pattern does not have a silicide layer disposed thereon, wherein the resistor spacer protrudes above the resistor pattern, and wherein the interlayer dielectric layer contacts a portion of the vertical inner sidewall of the resistor insulating spacers.