Method of fabricating SiGe Bi-CMOS device
View Patent ↗Provided is a method of fabricating a silicon germanium (SiGe) Bi-CMOS device. In the fabrication method, the source and drain of the CMOS device is formed using a silicon germanium (SiGe) heterojunction, instead of silicon, thereby preventing a leakage current resulting from a parasitic bipolar operation. Further, since the source and drain is connected with an external interconnection through the nickel (Ni) silicide layer, the contact resistance is reduced, thereby preventing loss of a necessary voltage for a device operation and accordingly, making it possible to enable a low voltage and low power operation and securing a broad operation region even in a low voltage operation of an analogue circuit.
1. A method of fabricating a silicon germanium (SiGe) Bi-CMOS device having a heterojunction bipolar transistor and a CMOS (Complementary Metal Oxide Semiconductor) transistor, the method comprising the steps of:
forming a sub-collector region in a substrate of a bipolar transistor region, and forming well regions in the substrate of a CMOS transistor region, respectively;
growing silicon epitaxial layers on the substrate of the sub-collector region and the well regions;
forming a collector and a collector plug in the silicon epitaxial layers of the bipolar transistor region, respectively, and implanting ions for controlling a threshold voltage into the silicon epitaxial layers of the CMOS transistor region;
forming a gate oxide layer on the substrate of the CMOS transistor region, and forming a first epitaxial layer on the collector and the gate oxide layer;
forming an emitter on the first epitaxial layer of the collector, and forming a gate on the gate oxide layer;
implanting impurity ions into the first epitaxial layer at both sides of the gate to form a LDD (Lightly Doped Drain) region, and implanting impurity ions into the collector at both sides of the emitter to form an external base layer;
forming spacers at both sidewalls of the emitter and the gate, respectively, and forming a second epitaxial layer on the first epitaxial layer, the emitter, the collector plug, the gate, and the LDD region;
forming a source and a drain in the second epitaxial layer at both sides of the gate; and
depositing and heat treating a nickel (Ni) layer on an entire surface of the resultant structure to form a nickel silicide layer on the second epitaxial layer, the emitter, the collector plug, the gate, and the source and drain, and removing the nickel (Ni) layer remaining without reaction.
2. The method as recited in claim 1 , wherein the first epitaxial layer is formed of a buffer layer, a SiGe layer, and a cap layer, and the buffer layer and the cap layer are formed of an undoped silicon layer.
3. The method as recited in claim 1 , wherein the second epitaxial layer is formed by a selective epitaxial growth (SEG) process.
4. The method as recited in claim 3 , wherein the second epitaxial layer is grown using gases such as SiH 2 Cl 2 , GeH 4 , HCl, and H 2 , at a predetermined pressure and at a temperature of 650 to 700° C., to have a thickness of 1000 to 3000 Å.
5. The method as recited in claim 1 , wherein the nickel (Ni) layer is deposited to a thickness of 500 to 1000 Å using a sputtering process.
6. The method as recited in claim 1 , wherein the heat-treatment is performed at a temperature of 300 to 600° C.
7. The method as recited in claim 1 , further comprising the step of, after the deposition of the nickel (Ni) layer, forming a cap layer on the nickel (Ni) layer in order to prevent oxidation of the nickel (Ni) layer.
8. The method as recited in claim 7 , wherein the cap layer is formed of TiN.
9. The method as recited in claim 1 , wherein the nickel (Ni) layer is removed by a wet etching process using a one-to-one solution of H 2 SO 4 and H 2 O 2 .
10. The method as recited in claim 1 , wherein in the step of removing the nickel (Ni) layer, the nickel (Ni) layer is not removed on the source and drain.