IP Library Granted Patent US 7,115,475
Granted Patent B2
US 7,115,475 · App. 11/002,638 · Granted Oct 3, 2006

Method of manufacturing semiconductor device

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 7,115,475
App. No.
11/002,638
Granted
Oct 3, 2006
Kind
B2
Abstract

A method of manufacturing a semiconductor device in which a trench groove is formed in a first conductivity type semiconductor layer, and a second conductivity type semiconductor layer is epitaxially grown so as to bury the trench groove. The second conductivity type semiconductor layer is then removed until a surface of the first conductivity type semiconductor layer is exposed. The first conductivity type semiconductor layer is epitaxially grown on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer such that the thickness of the first conductivity type semiconductor layer increases by a length which is substantially the same as a depth of the trench groove. The first conductivity type semiconductor layer is selectively removed such that the second conductivity type semiconductor layer is exposed, and the epitaxially growing of the second conductivity type semiconductor layer is repeated through selectively removing the first conductivity type semiconductor layer.

Claims (7)

1. A method of manufacturing a semiconductor device having a super junction structure with a first conductivity type semiconductor layer on which a trench groove whose aspect ratio is R is provided and a second conductivity type semiconductor layer which is buried in the trench groove, the method of manufacturing the semiconductor device comprising:

forming a trench groove having an aspect ratio of R/N, N being a natural number greater than 1, in a first conductivity type semiconductor layer;

epitaxially growing a second conductivity type semiconductor layer so as to bury the trench groove;

removing the second conductivity type semiconductor layer until a surface of the first conductivity type semiconductor layer is exposed;

epitaxially growing the first conductivity type semiconductor layer on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer such that the thickness of the first conductivity type semiconductor layer increases by a length which is substantially the same as a depth of the trench groove formed by said first process;

selectively removing the first conductivity type semiconductor layer such that the second conductivity type semiconductor layer which is buried in the trench groove formed by said first process is exposed; and

repeating said epitaxially growing the second conductivity type semiconductor layer through selectively removing the first conductivity type semiconductor layer N−1 times.

Priority Claims (1)
JP 2002-074633 · Mar 18, 2002 · national
Continuity (2)
Division 1038849800 · Mar 17, 2003
Related Publication 20050098826A1 · May 12, 2005