Semiconductor memory device for storing multivalued data
Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction.
1. A semiconductor memory device comprising:
a memory cell array configured by arranging a plurality of memory cells in a matrix, each of which is capable of having one of an 2 n (n is a natural number equal to 2 or more) number of threshold voltages and storing an n number of bits of data;
a plurality of bit lines connected to said plurality of memory cells arranged in the column direction;
a plurality of word lines connected to said plurality of memory cells arranged in the row direction;
a first and a second flag cell which are selected at the same time when the memory cells are selected by the word lines;
a write circuit which divides an n number of pages composed of an n number of bits stored in a plurality of memory cells selected by one of the word lines, into a first and a second area and, when writing data into the first area on a k-th page (2<=k<=n), writes the data into also the first flag cell and, when writing data into the second area on the k-th page, writes the data into also the second flag cell.
2. The semiconductor memory device according to claim 1 , wherein said plurality of memory cells arranged in the column direction are connected in series to form a NAND cell.
3. A semiconductor device comprising:
a memory cell storing a plurality of data by a state of n-values (n is a natural number equal to or larger than 2); and
a controller which sets the state of the memory cell to an h-value (h<=n) by raising a write voltage by a first voltage at a first write sequence, and which sets the state of the memory cell as an i-value (h<=i<=n) by raising the write voltage by a second voltage at a second write sequence;
wherein the first voltage is higher than the second voltage.
4. A semiconductor device comprising:
a memory cell array configured by arranging a plurality of memory cells in a matrix, each of which stores a plurality of data by a state of n-values (n is a natural number equal to or larger than 2); and
a controller which sets the state of a first memory cell of the memory cell array as an h-value (h<=n) by raising a write voltage by a first voltage at a first write sequence, which sets the state of a second memory cell adjacent to the first memory cell as an i-value (i<=n) by raising the write voltage by a second voltage at a second write sequence, which sets the state of the first memory cell as a j-value (h<=i<=n) by raising the write voltage by a third voltage at a third write sequence, and which sets the state of the second memory cell as a k-value (i<=k<=n) by raising the write voltage by a fourth voltage at a fourth write sequence;
wherein a relation among the first voltage, the second voltage, the third voltage and the fourth voltage is the second voltage>=the first voltage>=the fourth voltage>=the third voltage.
5. The device according to claim 4 , wherein the first memory cell and the second memory are connected to a same word line.
6. A semiconductor device comprising:
a memory cell array configured by arranging a plurality of memory cells in a matrix, each of which stores a plurality of data by a state of n-values (n is a natural number equal to or larger than 2); and
a controller which sets the state of a first memory cell of the memory cell array as an h-value (h<=n) by raising a write voltage by a first voltage at a first write sequence, which sets the state of a second memory cell adjacent to the first memory cell as an i-value (i<=n) by raising the write voltage by a second voltage at a second write sequence, which sets the state of a third memory cell adjacent to the first memory cell as the h-value by raising the write voltage by the first voltage at a third write sequence, and which sets the state of the first memory cell as a j-value (h<=j<=n) by raising the write voltage by a third voltage at a fourth write sequence;
wherein a relation among the first voltage, the second voltage and the third voltage is the second voltage>=the first voltage>=the third voltage.
7. The device according to claim 6 , wherein the first memory cell and the second memory are connected to a same word line.
8. The device according to claim 6 , wherein a word line connected to the first memory cell and a word line connected to the third memory are adjacent to each other.
9. A semiconductor device comprising:
a memory cell array configured by arranging a plurality of memory cells in a matrix, each of which stores a plurality of data by a state of n-values (n is a natural number equal to or larger than 2); and
a controller which sets the state of a first memory cell of the memory cell array as an h-value (h<=n) by raising a write voltage by a first voltage at a first write sequence, which sets the state of a second memory cell adjacent to the first memory cell as the h-value by raising the write voltage by the first voltage at a second write sequence, and which sets the state of the first memory cell as an i-value (h<=i<=n) by raising the write voltage by the second voltage at a third write sequence;
wherein a relation between the first voltage and the second voltage is the first voltage>=the second voltage.
10. The device according to claim 9 , wherein a word line connected to the first memory cell and a word line connected to the second memory are adjacent to each other.