Transfer of cache lines on-chip between processing cores in a multi-core system
Cache coherency is maintained between the dedicated caches of a chip multiprocessor by writing back data from one dedicated cache to another without routing the data off-chip. Various specific embodiments are described, using write buffers, fill buffers, and multiplexers, respectively, to achieve the on-chip transfer of data between dedicated caches.
1. An apparatus, comprising:
an integrated circuit including:
a first processor with a first dedicated cache;
a second processor with a second dedicated cache; and
control logic, coupled to the first and second dedicated caches, having:
a first multiplexer coupled to the first and second caches to receive a first cache line from the first dedicated cache and to provide the first cache line to the second dedicated cache; and
a second multiplexer coupled to the first and second caches to receive a second cache line from the second dedicated cache and to provide the second cache line to the first dedicated cache.
2. The apparatus of claim 1 , wherein:
the control logic is to transfer the first cache line if the first cache line is a cache line in the first dedicated cache and not in the second dedicated cache.
3. The apparatus of claim 1 , wherein:
the control logic is to transfer the first cache line if the first cache line is a modified version of a particular cache line and the second dedicated cache contains an unmodified version of the particular cache line.
4. The apparatus of claim 1 , further comprising:
a coherency unit to perform snoop operations on the first and second dedicated caches.
5. The apparatus of claim 1 , wherein the integrated circuit further includes:
a shared cache coupled to the control logic, to the first dedicated cache, and to the second dedicated cache;
wherein the control logic is further to transfer a second cache line from the second dedicated cache to the first dedicated cache;
wherein the control logic includes a first write buffer to receive the first cache line from the first dedicated cache and to provide the first cache line to the shared cache, and further includes a second write buffer to receive the second cache line from the second dedicated cache and provide the second cache line to the shared cache;
wherein the shared cache is to provide the first cache line to the second dedicated cache and to provide the second cache line to the first dedicated cache.
6. An apparatus, comprising:
an integrated circuit including:
a first processor with a first dedicated cache;
a second processor with a second dedicated cache; and
control logic, coupled to the first and second dedicated caches, having:
a first fill buffer coupled to the first and second dedicated caches to receive a first cache line from the first dedicated cache and to provide the first cache line to the second dedicated cache; and
a second fill buffer coupled to the first and second dedicated caches to receive a second cache line from the second dedicated cache and to provide the second cache line to the first dedicated cache.
7. The apparatus of claim 6 , further comprising:
a coherency unit to perform snoop operations on the first and second dedicated caches.
8. The apparatus of claim 6 , wherein the integrated circuit further includes:
a shared cache coupled to the control logic, to the first dedicated cache, and to the second dedicated cache;
wherein the control logic is further to transfer a second cache line from the second dedicated cache to the first dedicated cache;
wherein the control logic includes a first write buffer to receive the first cache line from the first dedicated cache and to provide the first cache line to the shared cache, and further includes a second write buffer to receive the second cache line from the second dedicated cache and provide the second cache line to the shared cache;
wherein the shared cache is to provide the first cache line to the second dedicated cache and to provide the second cache line to the first dedicated cache.
9. A method, comprising:
transferring a first cache line directly from a first dedicated cache of a chip multi-processor to a first multiplexer within control logic coupled to the first cache in the chip multi-processor;
subsequently transferring the first cache line from the first multiplexer directly to a second dedicated cache of the chip multi-processor,
transferring a second cache line directly from the second dedicated cache to a second multiplexer within the control logic coupled to the second cache in the chip multi-processor; and
subsequently transferring the second cache line from the second multiplexer directly to the first dedicated cache.
10. A method, comprising:
transferring a first cache line directly from a first dedicated cache of a chip multi-processor to a first write buffer within control logic coupled to the first cache in the chip multi-processor;
subsequently transferring the first cache line from the first write buffer directly to a second dedicated cache of the chip multi-processor,
transferring a second cache line directly from the second dedicated cache to a second write buffer within the control logic coupled to the second cache in the chip multi-processor; and
subsequently transferring the second cache line from the second write buffer directly to the first dedicated cache.
11. A system, comprising:
a main memory,
a chip multiprocessor coupled to the main memory and including:
a first processor with a first dedicated cache;
a second processor with a second dedicated cache; and
control logic, coupled to the first and second dedicated caches, having:
a first multiplexer coupled to the first and second caches to receive a first cache line from the first dedicated cache and to provide the first cache line to the second dedicated cache; and
a second multiplexer coupled to the first and second caches to receive a second cache line from the second dedicated cache and to provide the second cache line to the first dedicated cache.
12. The system of claim 11 , wherein the chip multiprocessor further comprises:
a coherency unit to perform snoop operations on the first and second dedicated caches.
13. The system of claim 11 , wherein the chip multiprocessor further includes:
a shared cache coupled to the control logic and to the second dedicated cache to provide the first cache line to the second dedicated cache;
wherein the control logic includes a write buffer to receive the first cache line from the first dedicated cache and to provide the first cache line to the shared cache.