IP Library Granted Patent US 7,122,421
Granted Patent B2
US 7,122,421 · App. 11/098,070 · Granted Oct 17, 2006

Semiconductor device including a transistor and a capacitor having an aligned transistor and capacitive element

Assignee: Freescale Semiconductor, Inc.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,122,421
App. No.
11/098,070
Granted
Oct 17, 2006
Kind
B2
Abstract

A semiconductor ( 10 ) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor ( 75, 77, 79 ), that are connected by a via or conductive region ( 52 ) and interconnect ( 68, 99 ). The via or conductive region ( 52 ) contacts a bottom surface of a diffusion or source region ( 22 ) of the transistor and contacts a first ( 75 ) of the capacitor electrodes. A laterally positioned vertical via ( 32, 54, 68 ) and interconnect ( 99 ) contacts a second ( 79 ) of the capacitor electrodes. A metal interconnect or conductive material ( 68 ) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.

Claims (26)

1. A semiconductor device comprising:

a layer of material having a first surface and a second surface, the second surface opposite the first surface;

a transistor having a control electrode, a first current electrode and a second current electrode overlying the first surface, the control electrode positioned closer to the layer of material than the first current electrode and the second current electrode;

a first metal structure formed further away from the first surface of the layer of material than the transistor, at least a portion of the first metal structure overlying the transistor;

an insulating layer formed further away from the first surface of the layer of material than the first metal structure, overlying the first metal structure and at least a portion of the transistor; and

a second metal structure formed further away from the first surface of the layer of material than the insulating layer, the second metal structure overlying the insulating layer and at least a portion of the transistor;

wherein the first metal structure, the insulating layer, and the second metal structure form a capacitive element overlying the transistor, at least a portion of the capacitive element located on a line that is orthogonal to the first surface and through a portion of the transistor;

a first conductive path coupled between the first metal structure of the capacitive element and at least one of the first current electrode and the second current electrode for electrically connecting the capacitive clement and the transistor; and

a second conductive path coupled to the second metal structure of the capacitive element, the second conductive path extending both above and below the capacitive element, the second conductive path having a portion that is lateral to the transistor, the second conductive path providing connection to the capacitive element from above or below the capacitive element or both.

2. The semiconductor device of claim 1 , wherein the first conductive path comprises a plurality of conductive contiguous layers.

3. The semiconductor device of claim 2 , wherein the first conductive path connects one of the first current electrode and the second current electrode of the transistor to the first metal structure of the capacitive element.

4. The semiconductor device of claim 1 , wherein the first current electrode and second current electrode each comprise a diffusion formed in a semiconductor layer positioned between the control electrode and the first metal structure of the capacitive element.

5. The semiconductor device of claim 1 wherein both the first conductive path and the second conductive path extend above a plane of an upper surface of the capacitive element and both the first conductive path and the second conductive path extend below a plane of a lower surface of the capacitive element.

6. The semiconductor device of claim 1 , wherein the first conductive path comprises a plurality of connecting conductive layers, one of the connecting conductive layers for providing a back bias for the transistor.

7. A semiconductor device comprising:

a semiconductor substrate having a first surface and a second surface, the second surface opposite the first surface;

a transistor overlying the semiconductor substrate and having a control electrode, a first current electrode and a second current electrode formed above the first surface, the control electrode positioned closer to the semiconductor substrate than the first current electrode and the second current electrode;

a capacitor having a first electrode and a second electrode formed above the transistor and on a same side of the semiconductor substrate as the transistor, at least a portion of the capacitor located on a line that is orthogonal to the first surface and through a portion of the transistor;

a first conductive path connecting the first electrode of the capacitor to at least one of the first current electrode and the second current electrode of the transistor; and

a second conductive path connected to the second electrode of the capacitor and extending both above and below the capacitor to be at least lateral to the transistor, the second conductive path providing connection to the capacitor from above or below the capacitor or both.

8. A semiconductor device comprising:

a layer of material having a first surface and a second surface, the second surface opposite the first surface;

a transistor underlying the layer of material and having a control electrode, a first current electrode and a second current electrode below the first surface, the control electrode positioned closer to the layer of material than the first current electrode and the second current electrode;

a capacitor positioned below the transistor wherein at least a portion of the capacitive element located on a line that is orthogonal to the first surface and through the transistor;

a first conductive path comprising at least one conductive layer located between the capacitive element and at least one of the first current electrode and the second current electrode for electrically connecting the capacitive element and the transistor; and

a second conductive path connected to the second electrode of the capacitor and extending both above and below the capacitor to be at least lateral to the transistor, the second conductive path providing connection to the capacitor from above or below the capacitor or both.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
Continuity (3)
Division 1094675800 · Sep 22, 2004
Division 1064154400 · Aug 15, 2003
Related Publication 20050167782A1 · Aug 4, 2005