Semiconductor memory device with a stacked gate including a floating gate and a control gate and method of manufacturing the same

1. A semiconductor memory device comprising:

a first MOS transistor including a first gate electrode which is formed on a first element region enclosed by a first element isolating region formed in a semiconductor substrate with a first gate insulating film interposed between the first element region and the first gate electrode, an end portion of the first gate electrode in the gate width direction being located on the first element isolating region; and

a second MOS transistor including a second gate electrode which is formed on a second element region enclosed by a second element isolating region formed in the semiconductor substrate with a second gate insulating film at least twice as thick as the first gate insulating film interposed between the second element region and the second gate electrode, an end portion of the second gate electrode in the gate width direction being located on the second element isolating region, the upper part of each of the first and second element isolating regions being formed so as to project from the surface of the semiconductor substrate and have their corners curved, and the width from the position where the first element isolating region contacts the first gate insulating film to the top surface end of the first element isolating region being equal to the width from the position where the second element isolating region contacts the second gate insulating film to the top surface end of the second element isolating region.

2. The semiconductor memory device according to claim 1 , wherein the underside of a part of the first gate electrode located on the first element isolating region is lower than the top surface of the first gate insulating film;

the underside of a part of the second gate electrode located on the second element isolating region is lower than the top surface of the second gate insulating film; and

the height from the underside of the part of the first gate electrode to the top surface of the first gate insulating film is equal to the height from the underside of the part of the second gate electrode to the top surface of the second gate insulating film.

3. The semiconductor memory device according to claim 1 , wherein the top surface of the first element isolating region is lower than the top surface of the second element isolating region.

4. The semiconductor memory device according to claim 3 , wherein the difference between the top surface of the first element isolating region and that of the second element isolating region is equal to the width from the position where the first element isolating region contacts the first gate insulating film to the top surface end of the first element isolating region.

5. The semiconductor memory device according to claim 1 , wherein the film thickness difference between the first and second gate insulating films is 10 nm or more.

6. The semiconductor memory device according to claim 1 , further comprising

memory cells each of which has a third MOS transistor with a stacked gate including a floating gate and a control gate formed on the floating gate with an inter-gate insulating film interposed therebetween, and a fourth MOS transistor which has a drain connected to the source of the third MOS transistor;

a memory cell array in which the memory cells are arranged in a matrix;

word lines each of which connects commonly to the control gates of the third MOS transistors in a same row;

select gate lines each of which connects commonly to the gates of the fourth MOS transistors in a same row;

a first row decoder which selects any one of the select gate lines in a read operation; and

a second row decoder which selects any one of the word lines and applies a negative potential to the select gate line in a write operation.

7. The semiconductor memory device according to claim 6 , wherein the first row decoder includes

row address decode circuits which are provided for the select gate lines in a one-to-one correspondence, and each of which includes the first MOS transistor and decodes a row address signal to produce a row address decode signal;

level shift circuits which are provided for the select gate lines in a one-to-one correspondence and each of which raises the potential of the row address decode signal; and

the second MOS transistors which are provided for the select gate lines in a one-to-one correspondence and each of which has one end of its current path connected to the corresponding select gate line and the other end connected to the corresponding level shift circuit.

8. The semiconductor memory device according to claim 6 , further comprising

bit lines each of which connects commonly to the drains of the third MOS transistors in a same row;

source line which connects commonly to the sources of the fourth MOS transistors;

a column decoder which selects any of the bit lines; and

a source line driver which applies a potential to the source line.

9. A semiconductor memory device comprising:

a first MOS transistor including a first gate electrode which is formed on a first element region enclosed by a first element isolating region formed in a semiconductor substrate with a first gate insulating film interposed between the first element region and the first gate electrode, an end portion of the first gate electrode in the gate width direction being located on the first element isolating region; and

a second MOS transistor including a second gate electrode which is formed on a second element region enclosed by a second element isolating region formed in the semiconductor substrate with a second gate insulating film at least twice as thick as the first gate insulating film interposed between the second element region and the second gate electrode, an end portion of the second gate electrode in the gate width direction being located on the second element isolating region, the upper part of each of the first and second element isolating regions being formed so as to project from the surface of the semiconductor substrate, the face where the first element isolating region contacts the first gate insulating film and the side face of the upper part of the first element isolating region being in the same plane, and the face where the second element isolating region contacts the second gate insulating film and the side face of the upper part of the second element isolating region being in the same plane.

10. The semiconductor memory device according to claim 9 , wherein the film thickness difference between the first and second gate insulating films is 10 nm or more.

11. The semiconductor memory device according to claim 9 , further comprising

memory cells each of which has a third MOS transistor with a stacked gate including a floating gate and a control gate formed on the floating gate with an inter-gate insulating film interposed therebetween, and a fourth MOS transistor which has a drain connected to the source of the third MOS transistor;

a memory cell array in which the memory cells are arranged in a matrix;

word lines each of which connects commonly to the control gates of the third MOS transistors in a same row;

select gate lines each of which connects commonly to the gates of the fourth MOS transistors in a same row;

a first row decoder which selects any one of the select gate lines in a read operation; and

a second row decoder which selects any one of the word lines and applies a negative potential to the select gate line in a write operation.

12. The semiconductor memory device according to claim 11 , wherein the first row decoder includes

row address decode circuits which are provided for the select gate lines in a one-to-one correspondence, and each of which includes the first MOS transistor and decodes a row address signal to produce a row address decode signal;

level shift circuits which are provided for the select gate lines in a one-to-one correspondence and each of which raises the potential of the row address decode signal; and

the second MOS transistors which are provided for the select gate lines in a one-to-one correspondence and each of which has one end of its current path connected to the corresponding select gate line and the other end connected to the corresponding level shift circuit.

13. The semiconductor memory device according to claim 11 , further comprising:

bit lines each of which connects commonly to the drains of the third MOS transistors in a same row;

source line which connects commonly to the source of the fourth MOS transistors;

a column decoder which selects any of the bit lines; and

a source line driver which applies a potential to the source line.