Method and apparatus for resolving additional load misses in a single pipeline processor under stalls of instructions not accessing memory-mapped I/O regions
An in-order single-issue microprocessor detects data cache misses generated by instructions behind a stalled instruction in the microprocessor pipeline and issues memory requests on the processor bus for the missing data so as to overlap with resolution of the stalled instruction, which may also be a cache miss. The data cache has pipeline stages that parallel portions of the main microprocessor pipeline. Replay buffers are employed to save the state, i.e., instructions and associated data addresses, of the parallel data cache stages so that instructions above the stalled instruction can continue to proceed down through the data cache and access the cache memory to generate cache misses. The data cache pipeline stages are restored upon detection that the stall will terminate. The bus requests for the missing data are issued only if the stalled instruction does not access a memory-mapped I/O region of the memory address space.
1. A single-issue in-order pipelined microprocessor for accessing data stored in a memory coupled to the microprocessor by a bus, the microprocessor comprising:
a plurality of buffers, configured to receive data from the memory on the bus;
a data cache, coupled to said plurality of buffers;
control logic, coupled to said data cache and said plurality of buffers, configured to determine whether one or more instructions following a stalled instruction in the microprocessor pipeline specify data missing in the data cache; and
a plurality of descriptors, coupled to said control logic, for specifying memory-mapped I/O regions of a memory address space of the microprocessor;
wherein said control logic is further configured to allocate one or more of said plurality of buffers to receive said missing data and to issue one or more requests on the bus for said missing data during resolution of said stalled instruction;
wherein said control logic is further configured to issue said one or more requests on the bus for said missing data only if said stalled instruction does not access a memory-mapped I/O region of said memory address space.
2. The microprocessor of claim 1 , further comprising a bus interface unit, coupled to said control logic, for interfacing with the bus.
3. The microprocessor of claim 2 , wherein said bus interface unit is adapted for communication with a socket 370 bus.
4. The microprocessor of claim 2 , wherein said bus interface unit is adapted for communication with a socket 7 bus.
5. The microprocessor of claim 1 , further comprising:
a second plurality of buffers, coupled to said control logic, configured to provide data to the memory on the bus;
wherein said control logic is configured to determine whether said stalled instruction is stalled due to lack of availability of one of said second plurality of buffers.
6. A method for resolving misses of a data cache in a single-issue in-order pipelined microprocessor during stalls of the microprocessor pipeline, the method comprising:
detecting a stall condition in said pipeline generated by an instruction issued by the single-issue microprocessor;
saving state information associated with a plurality of instructions issued subsequent to said instruction in response to said detecting said stall condition;
determining whether one or more of said plurality of instructions specifies data missing in the data cache during said stall condition;
issuing one or more requests on a bus coupling the microprocessor to a memory for said missing data in response to said determining; and
issuing a request on said bus to said memory for data specified by said instruction prior to said issuing said one or more requests for said missing data.
7. The method of claim 6 , further comprising:
receiving said data specified by said instruction from said bus prior to receiving said missing data.
8. The method of claim 7 , further comprising:
allocating a buffer for receiving said data specified by said instruction prior to allocating a buffer for receiving said missing data.
9. The method of claim 6 , further comprising:
determining whether one or more of said plurality of instructions specifies data missing in the data cache during said stall condition; and determining whether one or more of said plurality of instructions specifies data in the data cache after termination of said stall condition.
10. The method of claim 9 , wherein said determining whether one or more of said plurality of instructions specifies data in the data cache after termination of said stall condition comprises providing said plurality of data addresses to a cache memory in the data cache.
11. The method of claim 6 , wherein said saving said state information comprises saving a plurality of data addresses specified by said plurality of instructions.
12. A single-issue in-order pipelined microprocessor for accessing data stored in a memory coupled to the microprocessor by a bus, the microprocessor comprising:
a first plurality of buffers, configured to receive data from the memory on the bus;
a data cache, coupled to said first plurality of buffers;
control logic, coupled to said data cache and said first plurality of buffers, configured to determine whether one or more instructions following a stalled instruction in the microprocessor pipeline specify data missing in the data cache; and
a second plurality of buffers, coupled to said control logic, configured to provide data to the memory on the bus;
wherein said control logic is further configured to allocate one or more of said first plurality of buffers to receive said missing data and to issue one or more requests on the bus for said missing data during resolution of said stalled instruction;
wherein said control logic is further configured to determine whether said stalled instruction is stalled due to lack of availability of one of said second plurality of buffers.
13. The microprocessor of claim 12 , further comprising a bus interface unit, coupled to said control logic, for interfacing with the bus.
14. The microprocessor of claim 13 , wherein said bus interface unit is adapted for communication with a socket 370 bus.
15. The microprocessor of claim 13 , wherein said bus interface unit is adapted for communication with a socket 7 bus.
16. The microprocessor of claim 12 , further comprising:
a plurality of descriptors, coupled to said control logic, for specifying memory-mapped I/O regions of a memory address space of the microprocessor;
wherein said control logic is further configured to issue said one or more requests on the bus for said missing data only if said stalled instruction does not access a memory-mapped I/O region of said memory address space.