Semiconductor integrated circuit
An apparatus and method to reduce, during standby time, electric power caused by the leakage current flowing through a storage transistor in a 3-transistor dynamic cell. Source electrodes of storage transistors in a plurality of 3-transistor dynamic cells constituting a memory array are connected, and a switch is provided between the source electrode and a power supply terminal. The leakage current during the standby time is interrupted by bringing the switch into a conducting state during the active time, and by bringing the switch into a nonconducting state during the standby time.
1. A semiconductor integrated circuit comprising:
a memory cell including:
a storage transistor for storing an electric charge in a gate capacitance;
a write transistor for writing the electric charge from a write bit line to a gate electrode of the storage transistor; and
an access transistor for controlling conduction between a read bit line and a drain of the storage transistor; and
a switching element provided between a source electrode of the storage transistor and a power supply potential;
wherein said switching element controls the source electrode of the storage transistor so that in a standby state the source electrode stays in a floating state, and in a read operation state the potential of the source electrode becomes the power supply potential.
2. A semiconductor integrated circuit according to claim 1 , having a plurality of said memory cells and further comprising:
a plurality of write word lines extending in a first direction;
a plurality of read word lines extending in the first direction;
a plurality of read bit lines extending in a second direction that intersects the first direction; and
a plurality of write bit lines extending in the second direction;
wherein:
in each of the plurality of memory cells, a gate of the write transistor is connected to one of the plurality of write word lines, one of source/drain terminals of the write transistor is connected to one of the plurality of write bit lines, a gate of the access transistor is connected to one of the plurality of read word lines, one of source/drain terminals of the access transistor is connected to one of the plurality of read bit lines, the other of the source/drain terminals of the write transistor is connected to a gate electrode of the storage transistor, and a drain of the storage transistor is connected to the other of the source/drain terminals of the access transistor.
3. A semiconductor integrated circuit according to claim 2 , wherein:
a channel area of the write transistor is formed of a film having a film thickness of about 5 nm or less, said channel area being formed so as to surround a gate electrode of the write transistor through an insulated layer.
4. A semiconductor integrated circuit according to claim 3 , wherein:
a source/drain path of the write transistor is formed in a direction perpendicular to a direction in which a source/drain path of the storage transistor is formed.
5. A semiconductor integrated circuit according to claim 3 , wherein:
said switching element includes an N-channel MOS transistor having a source/drain path between the power supply potential and a source electrode of the storage transistor.
6. A semiconductor integrated circuit according to claim 2 , wherein:
said plurality of memory cells are provided with the switching element in common.
7. A semiconductor integrated circuit comprising:
a memory cell including:
a storage transistor for storing an electric charge in a gate capacitance;
a write transistor for writing the electric charge from a write bit line to a gate electrode of the storage transistor; and
an access transistor for controlling conduction between a read bit line and a drain of the storage transistor; and
a first circuit for changing the potential of a source electrode of the storage transistor in response to a state in which the semiconductor integrated circuit stays, either in a read operation state or in a standby state.
8. A semiconductor integrated circuit according to claim 7 , having a plurality of said memory cells and further comprising:
a plurality of write word lines extending in a first direction;
a plurality of read word lines extending in the first direction;
a plurality of read bit lines extending in a second direction that intersects the first direction; and
a plurality of write bit lines extending in the second direction;
wherein:
in each of the plurality of memory cells, a gate of the write transistor is connected to one of the plurality of write word lines, one of source/drain terminals of the write transistor is connected to one of the plurality of write bit lines, a gate of the access transistor is connected to one of the plurality of read word lines, one of source/drain terminals of the access transistor is connected to one of the plurality of read bit lines, the other of the source/drain terminals of the write transistor is connected to a gate electrode of the storage transistor, and a drain of the storage transistor is connected to the other of the source/drain terminals of the access transistor.
9. A semiconductor integrated circuit according to claim 8 , wherein:
a channel area of the write transistor is formed of a film having a film thickness of about 5 nm or less, said channel area being formed so as to surround a gate electrode of the write transistor through an insulated layer.
10. A semiconductor integrated circuit according to claim 9 , wherein:
a source/drain path of the write transistor is formed in a direction perpendicular to a direction in which a source/drain path of the storage transistor is formed.
11. A semiconductor integrated circuit according to claim 8 , wherein:
said first circuit includes an N-channel MOS transistor having a source/drain path between a power supply potential and a source electrode of the storage transistor, said first circuit controlling the source electrode of the storage transistor so that in a first state the source electrode stays in a floating state, and in a second state the potential of the source electrode becomes the power supply potential.
12. A semiconductor integrated circuit according to claim 11 , wherein:
said plurality of memory cells are provided with the first circuit in common.
13. A semiconductor integrated circuit comprising:
a memory cell including:
a storage transistor for storing an electric charge in a gate capacitance;
a write transistor for writing the electric charge from a write bit line to a gate electrode of the storage transistor; and
an access transistor for controlling the conduction between a read bit line and a drain of the storage transistor; and
a precharge transistor for charging a read bit line to a desired potential, a first electrode of the precharge transistor is connected to the read bit line, and a potential of a second electrode of the precharge transistor is changed in response to a state in which the semiconductor integrated circuit stays, either in an active state or in a standby state.
14. A semiconductor integrated circuit according to claim 13 , having a plurality of said memory cells and further comprising:
a plurality of write word lines extending in a first direction;
a plurality of read word lines extending in the first direction;
a plurality of read bit lines extending in a second direction that intersects the first direction;
a plurality of write bit lines extending in the second direction;
an X decoder for selecting among the plurality of read word lines and the plurality of write word lines; and
a Y decoder for selecting among the plurality of read bit lines and the plurality of write bit lines;
wherein:
in each of the plurality of memory cells, a gate of the write transistor is connected to one of the plurality of write word lines, one of source/drain terminals of the write transistor is connected to one of the plurality of write bit lines, a gate of the access transistor is connected to one of the plurality of read word lines, one of source/drain terminals of the access transistor is connected to one of the plurality of read bit lines, the other of the source/drain terminals of the write transistor is connected to a gate electrode of the storage transistor, and a drain of the storage transistor is connected to the other of the source/drain terminals of the access transistor.
15. A semiconductor integrated circuit according to claim 14 , wherein:
a channel area of the write transistor is formed of a film having a film thickness of about 5 nm or less, and is formed so as to surround a gate electrode of the write transistor through an insulated layer.
16. A semiconductor integrated circuit according to claim 15 , wherein:
a source/drain path of the write transistor is formed in a direction perpendicular to a direction in which a source/drain path of the storage transistor is formed.