Multi-structured Si-fin
Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produce a wider base portion. The disclosed semiconductor fin construction will also typically include a horizontal step region at the interface between the upper region and the lower region. Also disclosed are a series of methods of manufacturing semiconductor devices incorporating semiconductor fins having this dual construction and incorporating various combinations of insulating materials such as silicon dioxide and/or silicon nitride for forming shallow trench isolation (STI) structures between adjacent semiconductor fins.
1. A semiconductor device comprising:
a substrate;
a semiconductor fin extending generally upwardly from the substrate, wherein the semiconductor fin includes;
an upper portion, the upper portion having a first thickness t 1 and a substantially constant width w 0 ; and
a lower portion arranged between the upper portion and the substrate, the lower portion having a second thickness t 2 , a top width w 1 adjacent the upper portion and a bottom width w 2 , wherein w 1 <w 2 ; and
a gate electrode separated from the semiconductor fin by a dielectric material.
2. The semiconductor device according to claims 1 , wherein:
the gate electrode is separated from the upper portion of the semiconductor fin by a gate dielectric.
3. A semiconductor device according to claim 1 , wherein:
the width of the upper portion of the silicon fin and the top width of the lower portion of the silicon fin satisfy the equation w 0 =w 1 .
4. A semiconductor device according to claim 1 , wherein:
the upper portion has substantially vertical sidewalls; and
the lower portion has inclined sidewalls.
5. A semiconductor device according to claim 4 , wherein:
the sidewalls of the lower portion are inclined at least 3 degrees, but no more than 10 degrees, from vertical relative to a plane defined by a major surface of the substrate.
6. A semiconductor device according to claim 1 , wherein:
the width of the upper portion of the semiconductor fin and the top width of the lower portion of the silicon fin satisfy the relationship w 0 <w 1 ;
the first thickness and the second thickness satisfy the relationship t 1 ≦t 2 ;
and the semiconductor is silicon.
7. A semiconductor device according to claim 6 , wherein:
step regions are formed at the junction of the upper portion and the lower portion of the silicon fin, the step regions having a substantially horizontal surface and a width of about (w 1 −w 0 )/2.
8. A semiconductor device according to claim 6 , wherein:
the upper portion includes epitaxial silicon having a first doping profile; and
the lower portion includes silicon having a second doping profile, wherein the first and second doping profiles are not substantially identical.
9. A semiconductor device according to claim 6 , wherein:
the upper portion includes a surface region and an interior region, the surface region having a first dopant concentration and the interior region having a second dopant concentration, the second dopant concentration being lower than the first dopant concentration.
10. A semiconductor device according to claim 6 , wherein:
the semiconductor fin is characterized by an aspect ratio, the aspect ratio being defined by the relationship 2(t 1 +t 2 )/(w 2 +w 1 ), and further wherein the aspect ratio is between about 3:1 and about 10:1.