Data accumulation between data path having redrive circuit and memory device
Memory apparatus and methods accumulate data between a data path and a memory device. A memory agent may have a data accumulator between a redrive circuit and a memory device or interface. The data accumulator may accumulate data to or from the redrive circuit. Other embodiments are described and claimed.
1. A memory module comprising:
a first redrive circuit to receive a signal from a first point-to-point link and redrive the signal on a second point-to-point link;
a second redrive circuit to receive a second signal from a third point-to-point link and redrive the signal on a forth point-to-point link;
a memory device; and
a data accumulator coupled between the first redrive circuit and the memory device.
2. A memory module according to claim 1 wherein the point-to-point links comprise unidirectional links.
3. A memory module according to claim 1 wherein the data accumulator comprises a FIFO structure.
4. A memory module according to claim 1 wherein the memory device is coupled to the second redrive circuit.
5. A memory module according to claim 4 further comprising a second data accumulator coupled between the memory device and the second redrive circuit.
6. A memory module according to claim 1 wherein the memory device has a burst bandwidth that is greater than the bandwidth of the redrive circuit.
7. A memory module according to claim 1 wherein the data accumulator is constructed and arranged to accumulate data from the redrive circuit.
8. A memory module according to claim 1 wherein the data accumulator is constructed and arranged to accumulate data to the redrive circuit.
9. A memory buffer comprising:
a first redrive circuit to receive a first signal from a first point-to-point link and redrive the signal on a second point-to-point link;
a second redrive circuit to receive a second signal from a third point-to-point link and redrive the second signal on a fourth point-to-point link; and
a memory interface coupled to the first redrive circuit, wherein the memory interface comprises a data accumulator.
10. A memory buffer according to claim 9 wherein the point-to-point links comprise unidirectional links.
11. A memory buffer according to claim 9 wherein the data accumulator comprises a FIFO structure.
12. A memory buffer according to claim 9 further comprising a second data accumulator coupled between the memory interface and the second redrive circuit.
13. A memory system comprising:
a memory controller;
a memory agent having first and second redrive circuits; and
a first point-to-point link arranged to transmit a signal from the controller to the first redrive circuit of the memory agent;
wherein the memory agent comprises a data accumulator coupled to the first redrive circuit.
14. A memory system according to claim 13 wherein the point-to-point links comprise unidirectional links.
15. A memory system according to claim 13 wherein the data accumulator comprises a FIFO structure.
16. A memory system according to claim 13 further comprising a second point-to-point link arranged to transmit a signal from the memory agent to the controller.
17. A memory system according to claim 13 wherein the memory agent further comprises a second data accumulator coupled to the second redrive circuit.
18. A method for operating a memory agent comprising:
receiving a first signal on a first point-to-point link;
redriving the first signal on a second point-to-point link;
receiving a second signal on a third point-to-point link;
redriving the second signal on a forth point-to-point link;
accumulating write data from the first signal; and
delivering the write data to a memory device.
19. A memory system according to claim 18 wherein the point-to-point links comprise unidirectional links.
20. A method according to claim 18 wherein accumulating and delivering the write data comprises accumulating and delivering the write data in a FIFO sequence.
21. A method according to claim 18 further comprising:
accumulating read data from a memory device; and
transmitting the read data as the second signal.