Methods of fabricating non-volatile memory devices including nanocrystals
Non-volatile memory devices can be fabricated by forming a tunnel dielectric layer on a semiconductor substrate, subjecting the semiconductor substrate having the tunnel dielectric layer to an atomic layer deposition (ALD) process to form nanocrystals on the tunnel dielectric layer, removing the semiconductor substrate having the nanocrystals from an atomic layer deposition chamber, forming a control gate dielectric layer on the semiconductor substrate having the nanocrystal, and forming a control gate electrode on the semiconductor substrate having the control gate dielectric layer.
1. A method of manufacturing a non-volatile memory device, comprising:
forming a tunnel dielectric layer on a semiconductor substrate;
subjecting the semiconductor substrate having the tunnel dielectric layer to an atomic layer deposition (ALD) process to form nanocrystals on the tunnel dielectric layer;
forming a control gate dielectric layer on the semiconductor substrate having the nanocrystals; and
forming a control gate electrode on the semiconductor substrate having the control gate dielectric layer, wherein the atomic layer deposition process comprises:
injecting a first reactant into the atomic layer deposition chamber to form first reactant chemical adsorption points on the tunnel dielectric layer; and
removing a reaction residue in an atomic layer deposition chamber using a method selected from the group consisting of a method of exhausting the atomic layer deposition chamber, a method of injecting an inert gas into the atomic layer deposition chamber, a method of carrying out both the exhaustion and the injection, a method of sequentially carrying out the exhaustion and the injection at least one time, or a combination thereof.
2. The method according to claim 1 , wherein the first reactant is WF 6 , TiCl 4 , TiI 4 , Ti(OEt) 4 , TaCl 5 , CuCl, MoCl 5 , Ni(acac) 2 or a combination thereof.
3. The method according to claim 1 , wherein the first reactant is a compound comprising zirconium (Zr), hafnium (Hf), yttrium (Y), aluminum (Al) or a combination thereof.
4. The method according to claim 1 , wherein the first reactant is SiCl 4 , BCl 3 or a combination thereof.
5. The method according to claim 1 , further comprising forming reduction gas chemical adsorption points on the tunnel dielectric layer by injecting a reduction gas into the atomic layer deposition chamber before injecting the first reactant.
6. The method according to claim 5 , wherein the reduction gas comprises B 2 H 6 , SiH 4 , Si 2 H 6 , SiH 2 Cl 6 or a combination thereof.
7. The method according to claim 5 , wherein the reduction gas comprises at least two gases selected from the group consisting of B 2 H 6 , SiH 4 , Si 2 H 6 and SiH 2 Cl 6 , wherein the gases are sequentially supplied.
8. The method according to claim 1 , further comprising injecting a second reactant into the atomic layer deposition chamber after removing the reaction residue to react the second reactant with the first reactant chemical adsorption points.
9. The method according to claim 8 , wherein the second reactant comprises an ammonia gas.
10. The method according to claim 8 , wherein the second reactant comprises H 2 O, H 2 O 2 , O 2 or O 3 .
11. A method of manufacturing a non-volatile memory device, comprising:
forming a tunnel dielectric layer on a semiconductor substrate;
subjecting the semiconductor substrate having the tunnel dielectric layer to an atomic layer deposition (ALD) process to form nanocrystals on the tunnel dielectric layer, wherein the nanocrystals are selected from the group consisting of tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), molybdenum (Mo), nickel (Ni), a nitride thereof or combinations thereof;
forming a control gate dielectric layer on the semiconductor substrate having the nanocrystals; and
forming a control gate electrode on the semiconductor substrate having the control gate dielectric layer, wherein the tunnel dielectric layer comprises a silicon oxide layer having a thickness of about 25 Å.
12. The method according to claim 11 , wherein the ALD process is performed a plurality of times.
13. The method according to claim 11 , wherein the tunnel dielectric layer is formed of at least one layer comprising a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a hafnium oxide layer (HfO), a hafnium silicon oxide layer (HfSiO), a zirconium oxide layer (ZrO), a zirconium silicon oxide layer (ZrSiO), or a gadolinium oxide layer (GdO).
14. The method according to claim 11 , wherein the tunnel dielectric layer is formed of a stacked layer or a mixed material layer of at least two layers selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a hafnium oxide layer (HfO), a hafnium silicon oxide layer (HfSiO), a zirconium oxide layer (ZrO), a zirconium silicon oxide layer (ZrSiO), and a gadolinium oxide layer (GdO).
15. A method of manufacturing a non-volatile memory device, comprising:
forming a tunnel dielectric layer on a semiconductor substrate;
subjecting the semiconductor substrate having the tunnel dielectric layer to an atomic layer deposition (ALD) process to form nanocrystals on the tunnel dielectric layer, wherein the nanocrystals are oxide nanocrystals comprising zirconium (Zr), hafnium (Hf), yttrium (Y), aluminum (Al) or a combination thereof;
forming a control gate dielectric layer on the semiconductor substrate having the nanocrystals; and
forming a control gate electrode on the semiconductor substrate having the control gate dielectric layer, wherein the tunnel dielectric layer comprises a silicon oxide layer having a thickness of about 25 Å.
16. The method according to claim 15 , wherein the ALD process is performed a plurality of times.
17. The method according to claim 15 , wherein the tunnel dielectric layer is formed of at least one layer comprising a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a hafnium oxide layer (HfO), a hafnium silicon oxide layer (HfSiO), a zirconium oxide layer (ZrO), a zirconium silicon oxide layer (ZrSiO), or a gadolinium oxide layer (GdO).
18. The method according to claim 15 , wherein the tunnel dielectric layer is formed of a stacked layer or a mixed material layer of at least two layers selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a hafnium oxide layer (HfO), a hafnium silicon oxide layer (HfSiO), a zirconium oxide layer (ZrO), a zirconium silicon oxide layer (ZrSiO), and a gadolinium oxide layer (GdO).
19. A method of manufacturing a non-volatile memory device, comprising:
forming a tunnel dielectric layer on a semiconductor substrate;
subjecting the semiconductor substrate having the tunnel dielectric layer to an atomic layer deposition (ALD) process to form nanocrystals on the tunnel dielectric layer, wherein the nanocrystals are silicon nanocrystals, silicon nitride nanocrystals, boron nanocrystals, boron nitride nanocrystals or combinations thereof;
forming a control gate dielectric layer on the semiconductor substrate having the nanocrystals; and
forming a control gate electrode on the semiconductor substrate having the control gate dielectric layer, wherein the tunnel dielectric layer comprises a silicon oxide layer having a thickness of about 25 Å.
20. The method according to claim 19 , wherein the ALD process is performed a plurality of times.
21. The method according to claim 19 , wherein the tunnel dielectric layer is formed of at least one layer comprising a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a hafnium oxide layer (HfO), a hafnium silicon oxide layer (HfSiO), a zirconium oxide layer (ZrO), a zirconium silicon oxide layer (ZrSiO), or a gadolinium oxide layer (GdO).
22. The method according to claim 19 , wherein the tunnel dielectric layer is formed of a stacked layer or a mixed material layer of at least two layers selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a hafnium oxide layer (HfO), a hafnium silicon oxide layer (HfSiO), a zirconium oxide layer (ZrO), a zirconium silicon oxide layer (ZrSiO), and a gadolinium oxide layer (GdO).
23. A method of manufacturing a non-volatile memory device, comprising:
forming a tunnel dielectric layer on a semiconductor substrate;
injecting a reduction gas into an atomic layer deposition chamber to form reduction gas chemical adsorption points on the tunnel dielectric layer;
injecting a first reactant into an atomic layer deposition chamber to form first reactant chemical adsorption points on the tunnel dielectric layer thereby forming nanocrystals on the semiconductor substrate;
forming a control gate dielectric layer on the semiconductor substrate having the nanocrystals; and
forming a control gate electrode on the semiconductor substrate having the control gate dielectric layer.
24. The method according to claim 23 , wherein forming the reduction gas chemical adsorption points and forming the first reactant chemical adsorption points are repeated a plurality of times to form a desired size of nanocrystals.
25. The method according to claim 23 , wherein the reduction gas comprises B 2 H 6 , SiH 4 , Si 2 H 6 , SiH 2 Cl 6 or a combination thereof.
26. The method according to claim 23 , wherein the first reactant is WF 6 , TiCl 4 , TiI 4 , Ti(OEt) 4 , TaCl 5 , CuCl, MoCl 5 , Ni(acac) 2 or a combination thereof.
27. The method according to claim 23 , wherein the nanocrystals comprise tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), molybdenum (Mo) nickel (Ni) or a combination thereof.
28. The method according to claim 23 , further comprising injecting a second reactant into the atomic layer deposition chamber after forming the first reactant chemical adsorption points to react with the first reactant chemical adsorption points.
29. The method according to claim 23 , wherein the second reactant comprises an ammonia gas.
30. The method according to claim 23 , wherein the nanocrystals are a nitride comprising tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), molybdenum (Mo), nickel (Ni) or a combination thereof.
31. A method of manufacturing a non-volatile memory device, comprising:
forming a tunnel dielectric layer on a semiconductor substrate;
injecting B 2 H 6 into a atomic layer deposition chamber to form B 2 H 6 chemical adsorption points on the tunnel dielectric layer;
injecting WF 6 into the atomic layer deposition chamber to react WF 6 with the B 2 H 6 chemical adsorption points to provide tungsten (W) chemical adsorption points on the tunnel dielectric layer;
injecting an ammonia gas into the atomic layer deposition chamber so that the ammonia gas reacts with the tungsten (W) chemical adsorption points to provide tungsten nitride (WN) nanocrystals;
forming a control gate dielectric layer on the semiconductor substrate having the tungsten nitride (WN) nanocrystals; and
forming a control gate electrode on the semiconductor substrate having the control gate dielectric layer.
32. The method according to claim 31 , wherein reacting WF 6 with the B 2 H 6 chemical adsorption points to provide tungsten (W) chemical adsorption points on the tunnel dielectric layer and injecting an ammonia gas into the atomic layer deposition chamber so that the ammonia gas reacts with the tungsten (W) chemical adsorption points to provide tungsten nitride (WN) nanocrystals are repeated a plurality of times to form a desired size of tungsten nitride (WN) nanocrystals.