IP Library › Granted Patent US 7,148,567
Granted Patent B2
US 7,148,567 · App. 11/078,585 · Granted Dec 12, 2006

Semiconductor integrated circuit device

Assignee: Renesas Technology Corp.
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Quick Facts
Patent No.
US 7,148,567
App. No.
11/078,585
Granted
Dec 12, 2006
Kind
B2
Abstract

A semiconductor integrated circuit device has two semiconductor integrated circuit chips ( 20 and 30 ) respectively provided with a plurality of PADs ( 40 a –40 e, 41 a –41 e and 42 a –42 d ), a plurality of LEADs ( 50 a –50 d ) disposed around arrays of the semiconductor integrated circuit chips, and a plurality of bonding wires ( 60 a –60 e and 61 a –61 d ). The plurality of bonding wires are connected so as not to straddle one semiconductor integrated circuit chip ( 30 ) and allow wiring between the PADs ( 40 a –40 e ) of the other semiconductor integrated circuit chip ( 20 ) and the LEADs ( 50 a –50 d ).

Claims (13)

1. A semiconductor integrated circuit device, comprising:

a first semiconductor integrated circuit chip having a first electrode pad and a second electrode pad thereon;

a second semiconductor integrated circuit chip having a third electrode pad, a fourth electrode pad, a fifth electrode pad, a sixth electrode pad, a first wire electrically connecting the third electrode pad with the fourth electrode pad and a second wire electrically connecting the fifth electrode pad with the sixth electrode pad;

first and second leads;

a first bonding wire electrically connecting the first electrode pad with the third electrode pad;

a second bonding wire electrically connecting the second electrode pad with the fifth electrode pad;

a third bonding wire electrically connecting the fourth electrode pad with the first lead; and

a fourth bonding wire electrically connecting the sixth electrode pad with the second lead,

wherein the second semiconductor integrated circuit chip is arranged between the first semiconductor integrated circuit chip and the two leads,

wherein the first, second, third and fourth bonding wires do not straddle the second semiconductor integrated circuit chip, and

wherein the first wire crosses over the second wire.

2. The semiconductor device according to claim 1 , wherein the first electrode pad is electrically connected with the first lead only via the second semiconductor integrated circuit chip and the first and the third bonding wires, and wherein the second electrode pad is electrically connected with the second lead only via the second semiconductor integrated circuit chip and the second and the fourth bonding wires.

3. The semiconductor device according to claim 1 , wherein the second semiconductor integrated circuit chip includes interface functions between the first semiconductor integrated circuit chip and the first and the second leads.

Priority Claims (1)
JP 2001-369085 · Dec 3, 2001 · national
Continuity (2)
Continuation 1016018900 · Jun 4, 2002
Related Publication 20050156305A1 · Jul 21, 2005