System and method for implementing a hash algorithm
View Patent ↗A system and method for generating a message digest comprising: receiving a block of data and processing the block of data to achieve a message digest, the processing of the block of data including evaluating the block of data at time (t) in terms of time (t−x), wherein x is greater than or equal to 2.
1. A system generating a message digest, via a computer, said system comprising:
a memory storage location for receiving a block of data; and
a processor for processing said block of data to acquire said message digest, said processing of said block of data includes (i) evaluating said block of data at cycle=t in terms of cycle=(t−x), wherein x is greater than or equal to 2, and (ii) skipping one cycle per iteration in order to reduce a total number of cycles utilized for said processing of said block of data;
wherein said block of data is 512-bits;
wherein said message digest comprises 160-bits;
wherein said processor performs the following:
E ( t ) =C ( t− 2);
D ( t ) =S 30 [B ( t− 2)];
C ( t ) =S 30 [A ( t− 2)];
B ( t ) =S 5( A ( t− 2)) +ft ( B ( t− 2), C ( t− 2), D ( t− 2))+ E ( t− 2)+ Wt− 1 +Kt− 1; and
A
(
t
)
=
S5
(
S5
(
A
(
t
-
2
)
)
+
ft
(
B
(
t
-
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)
,
C
(
t
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,
D
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t
-
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+
E
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t
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+
Wt
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+
Kt
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ft
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A
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t
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S30
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B
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C
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=
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S30
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B
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C
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+
D
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+
WT
+
Kt
;
where A, B, C, D, E and W are words of a message, K is a constant word, f is a logical function, Sx represents a value circularly rotated by x bits;
said processor generating said message digest providing a message fingerprint for said data.
2. A system generating a message digest, via a computer, said system comprising:
a memory storage location for receiving a block of data; and
a processor for processing said block of data to acquire said message digest, said processing of said block of data includes (i) evaluating said block of data at cycle=t in terms of cycle=(t−x), wherein x is greater than or equal to 2, and (ii) skipping one cycle per iteration in order to reduce a total number of cycles utilized for said processing of said block of data;
wherein said block of data is 512-bits;
wherein said message digest comprises 128-bits;
wherein said processor performs the following:
D
[
t
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=
B
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t
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2
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+
(
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F
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and
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;
where A, B, C, D, E and W are words of a message, F is a function, M is a message block, T is a value from a table and S represents a shifting function;
said processor generating said message digest providing a message fingerprint for said data.
3. A system generating a message digest, via a computer, said system comprising:
a memory storage location for receiving a block of data; and
a processor for processing said block of data to acquire said message digest, said processing of said block of data includes;
if a message is less than m bits, then padding said message;
dividing said message into n words, said n words further comprising W[0] through W[n];
performing the following:
setting A equal to H 0 ,
setting B equal to H 1 ,
setting C equal to H 2 ,
setting D equal to H 3 ,
setting E equal to H 4 ;
establishing a counter for storing a value used in performing iteration, said counter being referred to as t;
setting t to an initial value;
setting a terminal value to an initial value;
for t not equal to said terminal value, iteratively performing steps a–e:
a. setting S equal to (T AND MASK);
b. if t is greater than or equal to a first defined value, then setting W[t]equal to a the value of a first shiftbit operation;
c. setting TEMP equal to the value of a second shiftbit operation+f(B,C,D)+E+W[s]+K t , wherein K t further comprises a constant value;
d. performing the following:
setting E equal to D,
setting D equal to C,
setting C equal to the value of a third shiftbit operation,
setting B equal to A,
setting A equal to TEMP;
e. incrementing t; and
performing the following:
setting H 0 equal to H 0 +A,
setting H 1 equal to H 1 +B,
setting H 2 equal to H 2 +C,
setting H 3 equal to H 3 +D,
setting H 4 equal to H 4 +E;
said processor generating said message digest providing a message fingerprint for said data.
4. The system as in claim 3 wherein:
m is equal to 512,
n is equal to 8, and further wherein each word is equal to 64 bits.
5. The system as in claim 4 wherein said first defined value is equal to 8.
6. The system as in claim 4 wherein W[0] is the leftmost word.
7. The system as in claim 4 wherein said MASK is equal to 0×00000007.
8. The system as in claim 4 wherein said initial value of t is equal to 0, further wherein said terminal value is less than or equal to 39.
9. The system as in claim 8 , further comprising the following:
if t is greater than or equal to 0 and t is less than or equal to 9, then perform the following:
setting f t (B,C,D) equal to (B AND C) OR (NOT(B) AND D),
setting f t (A,B,C) equal to (A AND B) OR (NOT(A) AND C);
if t is greater than or equal to 10 and t is less than or equal to 19, then perform the following:
setting f t (B,C,D) equal to (B XOR C XOR D),
setting f t (A,B,C) equal to (A XOR B XOR C);
if t is greater than or equal to 20 and t is less than or equal to 29, then perform the following:
setting f t (B,C,D) equal to (B AND C) OR (B AND D) OR (C AND D),
setting f t (A,B,C) equal to (A AND B) OR (A AND C) OR (B AND C); and
if t is greater than or equal to 30 and t is less than or equal to 39, then perform the following:
setting f t (B,C,D) equal to (B XOR C XOR D),
setting f t (A,B,C) equal to (A XOR B XOR C).
10. The system as in claim 9 wherein said first shiftbit operation, further comprises the following:
shift1bitleft( W[(t+6) AND MASK] XOR W[(t+3) AND MASK] XOR W[(t+1) and MASK] XOR W[(t+0)]).
11. The system as in claim 10 wherein said second shiftbit operation further comprises the following:
shift5bitsleft(A).
12. The system as in claim 11 wherein said third shiftbit operation further comprises the following:
shift30bitsleft(B).