Semiconductor memory and control method thereof allowing high degree of accuracy in verify operation
In write/erase verity operations of a memory transistor in a semiconductor memory, control of the semiconductor memory follows the following process. One main bit line is applied to be operative on the select side and another main bit line is applied to be operative on the reference side. On the select side, a sub bit line select transistor is turned on to select a sub bit line having connection to the memory transistor as a target for write/erase verify operations. The target memory transistor is turned on while the other memory transistors connected to the same sub bit line are turned off. On the reference side, a sub bit line select transistor is turned off to bring a sub bit line to a non-selected state.
1. A semiconductor memory comprising:
a first main bit line;
a first source line;
a first transistor;
a first sub bit line connected through said first transistor to said first main bit line;
a first memory transistor having one end connected to said first sub bit line and another end connected to said first source line;
a second main bit line;
a second source line;
a second transistor;
a second sub bit line connected through said second transistor to said second main bit line;
a second memory transistor having one end connected to said second sub bit line and another end connected to said second source line; and
an amplifier for differential amplification receiving respective currents flowing through said first and second main bit lines,
wherein said first transistor and said first memory transistor are turned on and no current flow is generated in said second memory transistor in verify operation of said first memory transistor,
wherein said second transistor is turned off in verify operation of said first memory transistor.
2. A semiconductor memory comprising:
a first main bit line;
a first source line;
a first transistor;
a first sub bit line connected through said first transistor to said first main bit line;
a first memory transistor having one end connected to said first sub bit line and another end connected to said first source line;
a second main bit line;
a second source line;
a second transistor;
a second sub bit line connected through said second transistor to said second main bit line;
a second memory transistor having one end connected to said second sub bit line and another end connected to said second source line; and
an amplifier for differential amplification receiving respective currents flowing through said first and second main bit lines,
wherein said first transistor and said first memory transistor are turned on and no current flow is generated in said second memory transistor in verify operation of said first memory transistor, and
wherein said second transistor is turned on and an off voltage is applied to a gate electrode of said second memory transistor, said off voltage being a voltage turning said second memory transistor off.
3. A method of controlling the semiconductor memory as defined in claim 2 , said method determining said voltage turning said second memory transistor off,
wherein said second memory transistor includes a plurality of second memory transistors, and
wherein distribution is prepared that describes the number of said second memory transistors with respect to threshold voltages,
said method comprising the steps of:
finding source-to-drain currents flowing in said second memory transistors with respect to each one of said threshold voltages when respective gate electrodes of said second memory transistors are subjected to application of a gate voltage of the same value;
calculating the products of the numbers obtained from said distribution and said currents with respect to each one of said threshold voltages, and obtaining the total sum of said products with respect to said threshold voltages; and
determining said gate voltage making said total sum to be smaller than a prescribed value as said off voltage.
4. A semiconductor memory comprising:
a first main bit line;
a first source line;
a first transistor;
a first sub bit line connected through said first transistor to said first main bit line;
a first memory transistor having one end connected to said first sub bit line and another end connected to said first source line;
a second main bit line;
a second source line;
a second transistor;
a second sub bit line connected through said second transistor to said second main bit line;
a second memory transistor having one end connected to said second sub bit line and another end connected to said second source line; and
an amplifier for differential amplification receiving respective currents flowing through said first and second main bit lines,
wherein said first transistor and said first memory transistor are turned on and no current flow is generated in said second memory transistor in verify operation of said first memory transistor, and
wherein said second transistor is turned on and an off bias is applied to said second memory transistor, said off bias being a back bias turning said second memory transistor off.
5. A method of controlling the semiconductor memory as defined in claim 4 , said method determining said back bias turning said second memory transistor off,
wherein said second memory transistor includes a plurality of second memory transistors, and
wherein distribution is prepared for each said back bias that describes the number of said second memory transistors with respect to threshold voltages,
said method comprising the steps of:
finding source-to-drain currents flowing in said second memory transistors with respect to each one of said threshold voltages when said second memory transistors are subjected to application of said back bias of the same value and respective gate electrodes of said second memory transistors are subjected to application of a gate voltage of the same value;
calculating the products of the numbers obtained from said distribution and said currents with respect to each one of said threshold voltages, and obtaining the total sum of said products with respect to said threshold voltages; and
determining said back bias making said total sum to be smaller than a prescribed value as said off bias.
6. A semiconductor memory, comprising:
a first main bit line;
a first source line;
a first transistor;
a first sub bit line connected through said first transistor to said first main bit line;
a first memory transistor having one end connected to said first sub bit line and another end connected to said first source line;
a second memory transistor connected in parallel to said first memory transistor, said second memory transistor having one end connected to said first sub bit line;
a second main bit line;
a second source line;
a second transistor;
a second sub bit line connected through said second transistor to said second main bit line;
a third memory transistor having one end connected to said second sub bit line and another end connected to said second source line; and
an amplifier for differential amplification receiving respective currents flowing through said first and second main bit lines,
wherein said second and third memory transistors are formed in the same well, and
wherein said first transistor and said first memory transistor are turned on and an off bias is applied to said well, said off bias being a back bias turning said second and third memory transistors off.
7. A method of controlling the semiconductor memory as defined in claim 6 , said method determining said back bias turning said second and third memory transistors off,
wherein said second memory transistor includes a plurality of second memory transistors and said third memory transistor includes a plurality of third memory transistors, and
wherein distribution is prepared for each said back bias that describes the number of said second and third memory transistors with respect to threshold voltages,
said method comprising the steps of:
finding source-to-drain currents flowing in said second and third memory transistors with respect to each one of said threshold voltages when said well is subjected to application of said back bias and respective gate electrodes of said second and third memory transistors are subjected to application of a gate voltage of the same value;
calculating the products of the numbers obtained from said distribution and said currents with respect to each one of said threshold voltages, and obtaining the total sum of said products with respect to said threshold voltages; and
determining said back bias making said total sum to be smaller than a prescribed value as said off bias.
8. A semiconductor memory comprising:
a first main bit line;
a first source line;
a first transistor;
a first sub bit line connected through said first transistor to said first main bit line;
a first memory transistor having one end connected to said first sub bit line and another end connected to said first source line;
a second memory transistor connected in parallel to said first memory transistor, said second memory transistor having one end connected to said first sub bit line;
a second main bit line; and
an amplifier for differential amplification receiving respective currents flowing through said first and second main bit lines,
wherein said first transistor and said first memory transistor are turned on and no current flow is generated in said second memory transistor in verify operation of said first memory transistor,
wherein an off voltage is applied to a gate electrode of said second memory transistor, said off voltage being a voltage turning said second memory transistor off.
9. A method of controlling the semi conductor memory as defined in claim 8 , said method determining said voltage turning said second memory transistor off,
wherein said second memory transistor includes a plurality of second memory transistors, and
wherein distribution is prepared that describes the number of said second memory transistors with respect to threshold voltages,
said method comprising the steps of:
finding source-to-drain currents flowing in said second memory transistors with respect to each one of said threshold voltages when respective gate electrodes of said second memory transistors are subjected to application of a gate voltage of the same value;
calculating the products of the numbers obtained from said distribution and said currents with respect to each one of said threshold voltages, and obtaining the total sum of said products with respect to said threshold voltages; and
determining said gate voltage making said total sum to be smaller than a prescribed value as said off voltage.
10. A semiconductor memory comprising:
a first main bit line;
a first source line;
a first transistor;
a first sub bit line connected through said first transistor to said first main bit line;
a first memory transistor having one end connected to said first sub bit line and another end connected to said first source line;
a second memory transistor connected in parallel to said first memory transistor, said second memory transistor having one end connected to said first sub bit line;
a second main bit line; and
an amplifier for differential amplification receiving respective currents flowing through said first and second main bit lines,
wherein said first transistor and said first memory transistor are turned on and no current flow is generated in said second memory transistor in verify operation of said first memory transistor, and
wherein an off bias is applied to said second memory transistor, said off bias being a back bias turning said second memory transistor off.
11. A method of controlling the semiconductor memory as defined in claim 10 , said method determining said back bias turning said second memory transistor off,
wherein said second memory transistor includes a plurality of second memory transistors, and
wherein distribution is prepared for each said back bias that describes the number of said second memory transistors with respect to threshold voltages,
said method comprising the steps of:
finding source-to-drain currents flowing in said second memory transistors with respect to each one of said threshold voltages when said second memory transistors are subjected to application of said back bias of the same value and respective gate electrodes of said second memory transistors are subjected to application of a gate voltage of the same value;
calculating the products of the numbers obtained from said distribution and said currents with respect to each one of said threshold voltages, and obtaining the total sum of said products with respect to said threshold voltages; and
determining said back bias making said total sum to be smaller than a prescribed value as said off bias.
12. A semiconductor memory comprising:
a first main bit line;
a first source line;
a first transistor;
a first sub bit line connected through said first transistor to said first main bit line;
a first memory transistor having one end connected to said first sub bit line and another end connected to said first source line;
a second memory transistor connected in parallel to said first memory transistor, said second memory transistor having one end connected to said first sub bit line;
a second main bit line; and
an amplifier for differential amplification receiving respective currents flowing through said first and second main bit lines,
wherein said first transistor and said first memory transistor are turned on and no current flow is generated in said second memory transistor in verify operation of said first memory transistor;
a second source line;
a second transistor;
a second sub bit line connected through said second transistor to said second main bit line; and
a third memory transistor having one end connected to said second sub bit line and another end connected to said second source line,
wherein no current flow is generated in said third memory transistor in verify operation of said first memory transistor.
13. The semiconductor memory according to claim 12 ,
wherein said second transistor is turned off in verify operation of said first memory transistor.
14. The semiconductor memory according to claim 12 ,
wherein said second transistor is turned on and an off voltage is applied to a gate electrode of said third memory transistor, said off voltage being a voltage turning said third memory transistor off.
15. A method of controlling the semiconductor memory as defined in claim 14 , said method determining said voltage turning said third memory transistor off,
wherein said third memory transistor includes a plurality of third memory transistors, and
wherein distribution is prepared that describes the number of said third memory transistors with respect to threshold voltages,
said method comprising the steps of:
finding source-to-drain currents flowing in said third memory transistors with respect to each one of said threshold voltages when respective gate electrodes of said third memory transistors are subjected to application of a gate voltage of the same value;
calculating the products of the numbers obtained from said distribution and said currents with respect to each one of said threshold voltages, and obtaining the total sum of said products with respect to said threshold voltages; and
determining said gate voltage making said total sum to be smaller than a prescribed value as said off voltage.
16. The semiconductor memory according to claim 12 ,
wherein said second transistor is turned on and an off bias is applied to said third memory transistor, said off bias being a back bias turning said third memory transistor off.
17. A method of controlling the semiconductor memory as defined in claim 16 , said method determining said back bias turning said third memory transistor off,
wherein said third memory transistor includes a plurality of third memory transistors, and
wherein distribution is prepared for each said back bias that describes the number of said third memory transistors with respect to threshold voltages,
said method comprising the steps of:
finding source-to-drain currents flowing in said third memory transistors with respect to each one of said threshold voltages when said third memory transistors are subjected to application of said back bias of the same value and respective gate electrodes of said third memory transistors are subjected to application of a gate voltage of the same value;
calculating the products of the numbers obtained from said distribution and said currents with respect to each one of said threshold voltages, and obtaining the total sum of said products with respect to said threshold voltages; and
determining said back bias making said total sum to be smaller than a prescribed value as said off bias.