IP Library Granted Patent US 7,162,572
Granted Patent B2
US 7,162,572 · App. 10/964,283 · Granted Jan 9, 2007

Memory and power efficient mechanism for fast table lookup

Assignee: Spans Logic Inc.
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Quick Facts
Patent No.
US 7,162,572
App. No.
10/964,283
Granted
Jan 9, 2007
Kind
B2
Abstract

A method of implementing classification CAM functionality using primarily RAM cells is disclosed.

Claims (13)

1. A method for implementing content-addressable memories, comprising the steps of:

a) separating entries of a content-addressable memory into different groups, wherein no more than one entry of any group can match any given input and wherein one of said different groups is grouped in such a way that the specification of which bits to compare is common to the whole group;

b) selecting a number of bit positions for each said group as distinguishing bit positions, wherein, the values of the entries in the selected distinguishing bit positions are sufficient to uniquely identify entries within each said group, and wherein the values of the entries at the selected distinguishing bit positions are not x (don't care) values within each said group;

c) configuring a bit selector circuit with the selected distinguishing bit positions,

d) configuring an entry selector circuit with values from the entries at the distinguishing bit positions, wherein, the entry select circuit is a binary content-addressable memory, and

wherein, the entry selector circuit further comprises a multi-stage circuit to perform a matching function;

e) loading the entries into a specification memory at locations corresponding to the distinguishing bit position in the entry selector circuit;

f) selecting bits from the given input at locations that configured into the entry bit selector circuit

g) matching the value of the selected given input bits to at most one of the values configured into the entry select circuit;

h) reading an entry from the specification memory at the location corresponding to the matching location in the entry select circuit;

i) modifying the entry read from the specification memory;

j) comparing the modified entry against an input word; and

k) outputting results of the comparison.

Assignments (3)
MERGER Recorded Nov 19, 2012
From: SPANS LOGIC INC.
To: CISCO SYSTEMS, INC.
Reel/Frame 029323/0609 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2012
From: CISCO SYSTEMS, INC.
To: CISCO TECHNOLOGY, INC.
Reel/Frame 029323/0844 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2005
From: SOMASUNDARAM, MADIAN
To: SPANS LOGIC, INC.
Reel/Frame 015639/0542 →
Continuity (2)
Provisional Application 6051076100 · Oct 11, 2003
Related Publication 20050138279A1 · Jun 23, 2005