Semiconductor device
A wiring board includes a plurality of wiring layers, and one surface formed with a plurality of chip connecting electrodes and another surface formed with a plurality of external connecting electrodes of a semiconductor device. The wiring board has wiring layers and vias. The plurality of chip connecting electrodes include first chip connecting electrodes, each used for a first signal whose logic value changes, and second chip connecting electrodes, each used for a second signal that changes after a change timing of the first signal. A wiring layer in which wiring routing of paths extending from the first chip connecting electrodes to their corresponding first external connecting electrodes is performed, and a wiring layer in which wiring routing of paths extending from the second chip connecting electrodes disposed adjacent to the first chip connecting electrodes to their corresponding second external connecting electrodes is performed, are made different from each other.
1. A semiconductor device comprising:
a semiconductor chip mounted over a wiring board,
wherein the wiring board has a plurality of wiring layers and has one surface formed with a plurality of chip connecting electrodes connected to the semiconductor chip and the other surface formed with a plurality of external connecting electrodes of the semiconductor device, said wiring board including wirings formed in the wiring layers and vias that connect the wirings among the wiring layers to connect the chip connecting electrodes and external connecting electrodes associated with one another,
wherein the plurality of chip connecting electrodes include first chip connecting electrodes each used in an interface for a first signal whose logic value changes in a predetermined timing, and second chip connecting electrodes each used in an interface for a second signal having a timing at which a logic value thereof changes after the change timing of the first signal, and
wherein a wiring layer in which wiring routing of paths extending from the first chip connecting electrodes to their corresponding first external connecting electrodes is principally performed, and a wiring layer in which wiring routing of paths extending from the second chip connecting electrodes disposed adjacent to the first chip connecting electrodes to their corresponding second external connecting electrodes is principally performed, are made different from each other.
2. A semiconductor device according to claim 1 , wherein the different wiring layers are respectively disposed over a surface of the wiring board and a back surface thereof with a wiring layer having a power supply plane and a wiring layer having a ground plane being interposed therebetween.
3. A semiconductor device according to claim 2 , wherein wirings for the paths extending from the first chip connecting electrodes to their corresponding first external connecting electrodes in one wiring layer, and wirings for the paths extending from the second chip connecting electrodes disposed adjacent to the first chip connecting electrodes to their corresponding second external connecting electrodes in the other wiring layer respectively have layouts that intersect between the wiring layers.
4. A semiconductor device according to claim 2 , wherein vias each connected to the ground plane are respectively individually adjacent to vias for the paths extending from the first chip connecting electrodes to their corresponding first external connecting electrodes and vias for the paths extending from the second chip connecting electrodes disposed adjacent to the first chip connecting electrodes to their corresponding second external connecting electrodes.
5. A semiconductor device according to claim 1 , wherein the first signal is input data, and the second signal is an output clock.
6. A semiconductor device according to claim 5 , wherein the output clock is a free running echo clock, and the semiconductor chip is a synchronous SRAM.
7. A semiconductor device according to claim 1 , wherein the first signal is an output clock, and the second signal is output data.
8. A semiconductor device according to claim 7 , wherein the output clock is a data strobe signal, and the semiconductor chip is a data processor having a synchronous DRAM interface.
9. A semiconductor device according to claim 1 , wherein the semiconductor chip has a plurality of bump electrodes respectively connected to the plurality of chip connecting electrodes, and second bump electrodes corresponding to the second chip connecting electrodes are located at an end of an array of first bump electrodes corresponding to the first chip connecting electrodes.
10. A semiconductor device comprising:
a semiconductor chip mounted over a wiring board,
wherein the wiring board has a plurality of wiring layers and has one surface formed with a plurality of chip connecting electrodes connected to the semiconductor chip and the other surface formed with a plurality of external connecting electrodes of the semiconductor device,
wherein the plurality of chip connecting electrodes include first chip connecting electrodes each used in an interface for a first signal whose logic value changes in a predetermined timing, and second chip connecting electrodes each used in an interface for a second signal having a timing at which a logic value thereof changes after the change timing of the first signal, and
wherein, of wirings for paths extending from the first chip connecting electrodes to their corresponding first external connecting electrodes and wirings for paths extending from the second chip connecting electrodes to their corresponding second external connecting electrodes, the wirings having sections arranged in parallel adjacent to one another are provided such that the sections thereof provided in the wiring layers different from one another become longer than the sections thereof arranged in parallel to one another within the same wiring layer.
11. A semiconductor device according to claim 10 , wherein the first signal is input data, and the second signal is an output clock.
12. A semiconductor device according to claim 11 , wherein the output clock is a free running echo clock, and the semiconductor chip is a synchronous SRAM.
13. A semiconductor device according to claim 10 , wherein the first signal is an output clock, and the second signal is output data.
14. A semiconductor device according to claim 13 , wherein the output clock is a data strobe signal, and the semiconductor chip is a data processor having a synchronous DRAM interface.
15. A semiconductor device comprising:
a semiconductor chip mounted over a wiring board,
wherein the wiring board has a plurality of wiring layers and has one surface formed with a plurality of chip connecting electrodes connected to the semiconductor chip and the other surface formed with a plurality of external connecting electrodes of the semiconductor device, said wiring board including wirings formed in the wiring layers and vias that connect the wirings among the wiring layers to connect the chip connecting electrodes and external connecting electrodes associated with one another,
wherein the plurality of chip connecting electrodes include first chip connecting electrodes each used in an interface for a first signal whose logic value changes in a predetermined timing, and second chip connecting electrodes each used in an interface for a second signal having a timing at which a logic value thereof changes after the change timing of the first signal, and
wherein vias each connected to the ground plane are respectively individually adjacent to vias for paths extending from the first chip connecting electrodes to their corresponding first external connecting electrodes and vias for paths extending from the second chip connecting electrodes disposed adjacent to the first chip connecting electrodes to their corresponding second external connecting electrodes.
16. A semiconductor device according to claim 15 , wherein the first signal is input data, and the second signal is an output clock.
17. A semiconductor device according to claim 16 , wherein the output clock is a free running echo clock, and the semiconductor chip is a synchronous SRAM.
18. A semiconductor device according to claim 15 , wherein the first signal is an output clock, and the second signal is output data.
19. A semiconductor device according to claim 18 , wherein the output clock is a data strobe signal, and the semiconductor chip is a data processor having a synchronous DRAM interface.