IP Library Granted Patent US 7,166,894
Granted Patent B2
US 7,166,894 · App. 10/507,757 · Granted Jan 23, 2007

Schottky power diode with SiCOI substrate and process for making such diode

Assignee: Commissariat a l'Energie Atomique
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Quick Facts
Patent No.
US 7,166,894
App. No.
10/507,757
Granted
Jan 23, 2007
Kind
B2
Abstract

The present invention relates to a power junction device including a substrate of the SiCOI type with a layer of silicon carbide ( 16 ) insulated from a solid carrier ( 12 ) by a buried layer of insulant ( 14 ), and including at least one Schottky contact between a first metal layer ( 40 ) and the surface layer of silicon carbide ( 16 ), the first metal layer ( 30 ) constituting an anode.

Claims (17)

1. Power junction device including a substrate of the SiCOI type with a layer of silicon carbide insulated from a solid carrier by a buried layer of insulant, and including at least one Schottky contact between a first metal layer and the surface of a layer of silicon carbide, the first metal layer constituting an anode, characterized in that the first metal layer is in contact with a flank of the layer of silicon carbide, forming an angle relative to a main surface of the layer of silicon carbide wherein the angle has a value between 20° and 80°.

2. The device according to claim 1 , including a surface layer of insulant coating the layer of silicon carbide, and wherein the first metal layer extends at least partially over flank of the surface layer of insulant coating the layer of silicon carbide and adjoining the flank of the surface layer of silicon carbide.

3. The device according to claim 1 , including a second metal layer in ohmic contact with the layer of silicon carbide, the second metal layer forming a cathode.

4. The device according to claim 1 , wherein the first metal layer extends as far as the solid carrier.

5. The device according to claim 1 , including at least one power diode and at least one transistor, the transistor having a channel formed in the layer of silicon carbide.

6. The device according to claim 1 , including a plurality of power diodes connected in series or in parallel.

7. The device according to claim 3 , wherein the first and second metal layers have comb-forming parts respectively, the comb-forming parts of the first and second metal layers being interdigitated.

8. A process for manufacturing a power diode on a SiCOI substrate with a layer of silicon carbide insulated from a solid silicon carrier by a buried layer of insulant, the process including the following stages:

a) the formation of an ohmic contact point on one surface of the layer of silicon carbide, opposite the buried layer of insulant,

b) the localized etching of the layer of silicon carbide outside an area of the ohmic contact so as to release at least one lateral flank on the layer of silicon carbide, and

c) the formation of a Schottky contact on the lateral flank.

9. The process according to claim 8 , wherein the localized etching is etching using a lithographic mask and a lithographic agent with restricted selectivity relative to the lithographic mask, so as to confer a slope on the lateral flank.

10. The process according to claim 8 , wherein stage a) includes the formation on the layer of silicon carbide of a surface layer of insulant.

11. The process according to claim 8 , wherein the surface layer of insulant is used as a lithographic mask during stage b.

12. The process according to claim 8 , wherein the Schottky contact is formed between a metal layer and the layer of silicon carbide, the metal layer being extended partly over the surface layer of insulant.

13. The process according to claim 8 , wherein the Schottky contact is formed between a metal layer and the layer of silicon carbide, the metal layer being extended as far as the solid carrier, through an opening previously provided in the buried layer of insulant.

14. The process according to claim 8 , wherein the stage of forming an ohmic contact point includes the formation of a doped zone in the layer of silicon carbide, then the deposition of a layer of metal in contact with a central part of the doped zone, by providing a shift between the layer of metal and the periphery of the doped zone.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2004
From: TEMPLIER, FRANCOIS; BILLON, THIERRY; DAVAL, NICOLAS
To: COMMISSARIAT A L'ENERGIE ATOMIQUE; S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES
Reel/Frame 016365/0777 →
Priority Claims (1)
FR 02 03165 · Mar 14, 2002 · national
Continuity (1)
Related Publication 20050161760A1 · Jul 28, 2005