IP Library › Granted Patent US 7,172,955
Granted Patent B2
US 7,172,955 · App. 11/287,405 · Granted Feb 6, 2007

Silicon composition in CMOS gates

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 7,172,955
App. No.
11/287,405
Granted
Feb 6, 2007
Kind
B2
Abstract

A semiconductor device comprises an n-type MIS transistor comprising a first gate insulating film and a first gate electrode including an MSi x film formed on the first gate insulating film, where M represents a metal element selected from tungsten and molybdenum and x is greater than 1, i.e., x>1; and a p-type MIS transistor comprising a second gate insulating film and a second gate electrode including an MSi y film formed on the second gate insulating film, where y is not less than 0 and less than 1, i.e., 0≦y<1.

Claims (11)

1. A method of manufacturing a semiconductor device, comprising:

forming an MSi y film, where M represents a metal element selected from tungsten and molybdenum and y is not less than 0 and less than 1, i.e., 0≦y<1, on a first gate insulating film within a first region in which an n-type MIS transistor is to be formed and on a second gate insulating film within a second region in which a p-type MIS transistor is to be formed; and

forming an MSi x film, where x is greater than 1, i.e., x>1, within the first region by allowing the MSi y film within the first region to react with silicon.

2. The method according to claim 1 , wherein forming the MSi x film comprises forming a silicon film on the MSi y film within the first region, and allowing the MSi y film within the first region to react with the silicon film by applying a heat treatment.

3. The method according to claim 1 , further comprising forming on the MSi x film a conductive film having a resistivity lower than that of the MSi x film.

4. The method according to claim 1 , wherein the value of x is not less than 2, i.e., x≧2.

5. A method of manufacturing a semiconductor device, comprising:

forming an MSi x film, where M represents a metal element selected from tungsten and molybdenum and x is greater than 1, i.e., x>1, on a first gate insulating film within a first region in which an n-type MIS transistor is to be formed and on a second gate insulating film within a second region in which a p-type MIS transistor is to be formed; and

forming an MSi y film, where y is not less than 0 and less than 1, i.e., 0≦y<1, within the second region by extracting silicon contained in the MSi x film within the second region.

6. The method according to claim 5 , wherein forming the MSi y film comprises forming a metal film on the MSi x film within the second region, and allowing the metal film to react with silicon contained in the MSi x film within the second region by applying a heat treatment.

7. The method according to claim 5 , wherein the value of x is not less than 2, i.e., x≧2.

Assignments (4)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
Priority Claims (2)
JP 2001-398180 · Dec 27, 2001 · national
JP 2002-344226 · Nov 27, 2002 · national
Continuity (2)
Division 1032611300 · Dec 23, 2002
Related Publication 20060081893A1 · Apr 20, 2006