Self-aligned contact for silicon-on-insulator devices
View Patent ↗A method for forming a self-aligned contact to an ultra-thin body transistor first providing an ultra-thin body transistor with source and drain regions operated by a gate stack; forming a contact spacer on the gate stack; forming a passivation layer overlying the transistor; forming a contact hole in the passivation layer exposing the contact spacer and the source/drain regions; filling the contact hole with an electrically conductive material; and establishing electrical communication with the source/drain region.
1. A method for forming a self-aligned contact to a multiple-gate transistor comprising the steps of:
providing a multiple-gate transistor comprising a source region and a drain region separated by a gate stack;
forming a contact spacer on said gate stack;
forming a passivation layer overlying said multiple-gate transistor;
forming a contact hole in said passivation layer exposing said contact spacer and said source/drain region; and
filling said contact hole with an electrically conductive material for establishing electrical communication with said source/drain region.
2. The method of claim 1 further comprising the step of providing said multiple-gate transistor in a double-gate transistor.
3. The method of claim 1 further comprising the step of providing said multiple-gate transistor in a triple-gate transistor.
4. The method of claim 1 further comprising the step of providing said multiple-gate transistor in an omega field-effect transistor.
5. The method of claim 1 , wherein a gate electrode of said gate stack comprises a gate material selected from the group consisting of poly-crystalline silicon and poly-crystalline silicon-germanium.
6. The method of claim 1 , wherein a gate electrode of said gate stack comprises a gate material that is a refractory metal.
7. The method of claim 1 , wherein said gate stack comprises a gate electrode and a gate capping layer.
8. The method of claim 7 , wherein said gate capping layer comprises a dielectric.
9. The method of claim 7 , wherein said gate capping layer comprises silicon nitride.
10. The method of claim 7 , wherein said gate capping layer comprises a silicon nitride layer overlying a silicon oxide layer.
11. The method of claim 1 , wherein said contact spacer comprises a dielectric.
12. The method of claim 1 , wherein said contact spacer comprises silicon nitride.
13. The method of claim 1 , wherein said contact spacer is a composite spacer.
14. The method of claim 1 , wherein said contact spacer has a width between about 20 angstroms and about 5000 angstroms.
15. The method of claim 1 , wherein said passivation layer comprises silicon oxide.
16. The method of claim 1 , wherein said passivation layer has a thickness in the range between about 500 angstroms and about 3000 angstroms.
17. The method of claim 1 , wherein said electrically conductive material includes tungsten.
18. The method of claim 1 , wherein said electrically conductive material is a nitride selected from the group consisting of titanium nitride and tantalum nitride.
19. A self-aligned contact device comprising:
a multiple-gate transistor comprising a source and a drain separated by a gate stack;
a contact spacer formed on the side of the gate stack; and
an electrically conductive contact in contact with said contact spacer and in electrical communication with said source and drain.
20. The device of claim 19 , wherein said multiple-gate transistor is a double-gate transistor.
21. The device of claim 19 , wherein said multiple-gate transistor is a triple-gate transistor.
22. The device of claim 19 , wherein said multiple-gate transistor is an omega field-effect transistor.
23. The device of claim 19 , wherein a gate electrode of said gate stack comprises a material selected from the group consisting of poly-crystalline silicon and poly-crystalline silicon-germanium.
24. The device of claim 19 , wherein a gate electrode of said gate stack comprises a refractory metal.
25. The device of claim 19 , wherein said gate stack comprises a gate electrode and a gate capping layer.
26. The device of claim 25 , wherein said gate capping layer comprises a dielectric.
27. The device of claim 25 , wherein said gate capping layer comprises silicon nitride.
28. The device of claim 25 , wherein said gate capping layer comprises a silicon nitride layer overlying a silicon oxide layer.
29. The device of claim 19 , wherein said contact spacer comprises a dielectric.
30. The device of claim 19 , wherein said contact spacer comprises silicon nitride.
31. The device of claim 19 , wherein said contact spacer is a composite spacer.
32. The device of claim 19 , wherein said contact spacer has a width between about 20 angstroms and about 5000 angstroms.
33. The device of claim 19 , wherein said electrically conductive contact is formed of tungsten.
34. The device of claim 19 , wherein said electrically conductive contact is formed of a nitride selected from the group consisting of titanium nitride and tantalum nitride.