Semiconductor device having high drive current and method of manufacturing thereof

1. A semiconductor circuit, comprising:

a first semiconductor device in a substrate, the first semiconductor device comprises:

a gate structure;

a spacer disposed on sidewalls of the gate structure, the spacer having a first thickness;

raised source and drain regions disposed on either side of the gate structure;

a second semiconductor device in the substrate and electrically isolated from the first semiconductor device, the second semiconductor device comprises:

a gate structure;

a spacer disposed on sidewalls of the gate structure, the spacer having a second thickness less than the first thickness of the spacer of the first semiconductor device;

recessed source and drain regions disposed on either side of the gate structure, wherein the recessed source and drain regions have a top surface recessed below a top surface of the substrate prior to formation of a contact on the recessed source and drain regions.

2. The semiconductor circuit of claim 1 , wherein the gate structure of the first semiconductor device has a height greater than that of the gate structure of the second semiconductor device.

3. The semiconductor circuit of claim 1 , wherein the raised source and drain regions comprises:

lightly doped drain regions; and

deeper more heavily doped regions.

4. The semiconductor circuit of claim 1 , wherein the gate structures of the first and second semiconductor device each comprises:

a gate dielectric layer disposed over the substrate; and

a gate electrode disposed over the gate dielectric layer.

5. The semiconductor circuit of claim 1 , wherein the spacer of the first and second semiconductor devices each comprises:

a shaped oxide layer over the gate structure;

a shaped nitride layer over the oxide layer.

6. The semiconductor circuit of claim 1 , wherein the spacers of the first and second semiconductor devices are L-shaped.

7. A semiconductor circuit, comprising:

a first semiconductor device in a substrate, the first semiconductor device comprises:

a gate structure;

a spacer disposed on sidewalls of the gate structure, the spacer having a first thickness;

raised source and drain regions disposed on either side of the gate structure;

a second semiconductor device in the substrate and electrically isolated from the first semiconductor device, the second semiconductor device comprises:

a gate structure;

a spacer disposed on sidewalls of the gate structure, the spacer having a second thickness less than the first thickness of the spacer of the first semiconductor device;

recessed source and drain regions disposed on either side of the gate structure,

wherein the spacer of the first semiconductor device comprises:

a liner oxide layer;

a nitride layer over the liner oxide layer;

a first oxide layer over the nitride layer; and

a second oxide layer over the first oxide layer.

8. A semiconductor circuit, comprising:

a first semiconductor device in a substrate, the first semiconductor device comprises:

a gate structure;

a spacer disposed on sidewalls of the gate structure, the spacer having a first thickness;

raised source and drain regions disposed on either side of the gate structure;

a second semiconductor device in the substrate and electrically isolated from the first semiconductor device, the second semiconductor device comprises:

a gate structure;

a spacer disposed on sidewalls of the gate structure, the spacer having a second thickness less than the first thickness of the spacer of the first semiconductor device;

recessed source and drain regions disposed on either side of the gate structure, wherein the spacer of the second semiconductor device comprises:

a liner oxide layer;

a nitride layer over the liner oxide layer; and

an oxide layer over the nitride layer.

9. The semiconductor circuit of claim 1 , wherein the spacer of the first and second semiconductor device comprises:

a liner oxide layer; and

a nitride layer over the liner oxide layer.

10. A semiconductor circuit, comprising:

a first semiconductor device in a substrate, the first semiconductor device comprises:

a gate structure;

a spacer disposed on sidewalls of the gate structure, the spacer having a first thickness;

raised source and drain regions disposed on either side of the gate structure;

a second semiconductor device in the substrate and electrically isolated from the first semiconductor device, the second semiconductor device comprises:

a gate structure;

a spacer disposed on sidewalls of the gate structure, the spacer having a second thickness substantially equal to the first thickness of the spacer of the first semiconductor device;

recessed source and drain regions disposed on either side of the gate structure, wherein the recessed source and drain regions have a top surface recessed below a top surface of the substrate prior to formation of a contact on the recessed source and drain regions.

11. The semiconductor circuit of claim 10 , wherein the gate structure of the first semiconductor device has a height greater than that of the gate structure of the second semiconductor device.

12. The semiconductor circuit of claim 10 , wherein the raised source and drain regions comprises:

lightly doped drain regions; and

deeper more heavily doped regions.

13. The semiconductor circuit of claim 10 , wherein the gate structures of the first and second semiconductor device each comprises:

a gate dielectric layer disposed over the substrate; and

a gate electrode disposed over the gate dielectric layer.

14. The semiconductor circuit of claim 10 , wherein the spacer of the first and second semiconductor devices each comprises:

a shaped oxide layer over the gate structure;

a shaped nitride layer over the oxide layer.

15. The semiconductor circuit of claim 10 , wherein the spacers of the first and second semiconductor devices are L-shaped.