Bootstrapped switch with an input dynamic range greater than supply voltage

1. A bootstrapping circuit capable of sampling inputs beyond supply voltage comprising:

a bootstrapped switch coupled between an input node and an output node;

a first transistor having a first end coupled to a control node of the bootstrapped switch;

a first capacitor having a first end coupled to a second end of the first transistor;

a second transistor coupled between the first end of the first transistor and a supply node, and having a control node coupled to a first clock signal node;

a third transistor coupled between the second end of the first transistor and the supply node;

a charge pump having an output coupled to a control node of the third transistor;

a level shifter having an output coupled to a second end of the first capacitor;

a fourth transistor cross coupled with the first transistor;

a fifth transistor having a second end coupled to a first end of the fourth transistor and having a control node coupled to the output of the level shifter; and

a sixth transistor coupled between a first end of the fifth transistor and a common node, and having a control node coupled to the first clock signal node.

2. The circuit of claim 1 further comprising a seventh transistor coupled between the supply node and a control node of the first transistor, and having a control node coupled to a second clock signal node.

3. The circuit of claim 2 wherein a signal on the second clock signal node is inverted from a signal on the first clock signal node.

4. The circuit of claim 1 further comprising a diode having a first end coupled to the output of the level shifter and a second end coupled to a control node of the first transistor.

5. The circuit of claim 2 further comprising a diode having a first end coupled to the output of the level shifter and a second end coupled to the control node of the first transistor.

6. The circuit of claim 1 further comprising an eighth transistor coupled between the control node of the bootstrapped switch and a common node.

7. The circuit of claim 5 further comprising an eighth transistor coupled between the control node of the bootstrapped switch and a common node, and having a control node coupled to the second clock signal node.

8. The circuit of claim 2 wherein the level shifter comprises:

a first level-shifter transistor coupled between the input node and the second end of the first capacitor, and having a backgate coupled to a second end of the first level-shifter transistor; and

a second level-shifter transistor coupled to the input node and cross-coupled with the first level-shifter transistor, and having a backgate coupled to the second end of the first level shifter transistor.

9. The circuit of claim 8 wherein the level shifter further comprises:

a third level-shifter transistor coupled between the second level-shifter transistor and a common node, and having a control node coupled to a third clock signal node; and

a fourth level-shifter transistor coupled between the first level-shifter transistor and the common node, and having a control node coupled to a fourth clock signal node.

10. The circuit of claim 8 wherein the level shifter further comprises:

a fifth level-shifter transistor coupled in parallel with the first level-shifter transistor and having a control node coupled to a third clock signal node; and

a sixth level-shifter transistor coupled in parallel with the second level-shifter transistor and having a control node coupled to a fourth clock signal node.

11. The circuit of claim 10 wherein a signal on the fourth clock signal node is inverted from a signal on the third clock signal node.

12. The circuit of claim 9 wherein the level shifter further comprises:

a fifth level-shifter transistor coupled in parallel with the first level-shifter transistor and having a control node coupled to the third clock signal node; and

a sixth level-shifter transistor coupled in parallel with the second level-shifter transistor and having a control node coupled to the fourth clock signal node.

13. The circuit of claim 12 wherein a signal on the fourth clock signal node is inverted from a signal on the third clock signal node.

14. The circuit of claim 8 further comprising a diode having a first end coupled to the second end of the first capacitor and a second end coupled to a control node of the first transistor.

15. The circuit of claim 14 further comprising a seventh transistor coupled between the supply node and a control node of the first transistor, and having a control node coupled to the second clock signal node.

16. The circuit of claim 9 further comprising a diode having a first end coupled to the second end of the first capacitor and a second end coupled to a control node of the first transistor.

17. The circuit of claim 16 further comprising a seventh transistor coupled between the supply node and a control node of the first transistor, and having a control node coupled to the second clock signal node.

18. The circuit of claim 1 wherein the charge pump comprises:

a first charge-pump transistor having a first end coupled to the supply node; and

a second charge-pump transistor having a first end coupled to the supply node and cross-coupled with the first charge-pump transistor.

19. The circuit of claim 18 wherein the charge pump further comprises:

a first charge-pump capacitor coupled between a second end of the first charge-pump transistor and a third clock signal node; and

a second charge-pump capacitor coupled between a second end of the second charge-pump transistor and a fourth clock signal node.

20. The circuit of claim 19 wherein a control node of the third transistor is coupled to a control node of the first charge-pump transistor.