IP Library › Granted Patent US 7,188,238
Granted Patent B2
US 7,188,238 · App. 10/442,486 · Granted Mar 6, 2007

Methods and apparatus to update a basic input/output system (BIOS)

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,188,238
App. No.
10/442,486
Granted
Mar 6, 2007
Kind
B2
Abstract

Methods and apparatus to update a basic input/output system (BIOS) are described herein. In an example method, a processor determines a storing characteristic associated with a BIOS component stored in a non-volatile memory, and determines an operating characteristic associated with the BIOS component. Based on the storing characteristic and the operating characteristic associated with the BIOS component, the processor determines boundaries of the BIOS component within the non-volatile memory.

Claims (39)

1. A method to update a basic input/output system (BIOS) comprising:

determining a storing characteristic associated with a BIOS component stored in a non-volatile memory;

determining whether the BIOS component is a shared BIOS component or a non-shared BIOS component;

determining boundaries of the BIOS component within the non-volatile memory based on the storing characteristic associated with the BIOS component and whether the BIOS component is a shared BIOS component or a non-shared BIOS component; and

updating the BIOS component within the boundaries.

2. A method as defined in claim 1 , wherein determining the storing characteristic associated with the BIOS component comprises querying for a partition identifier associated with a BIOS component stored in a flash memory.

3. A method as defined in claim 1 , wherein determining the storing characteristic associated with the BIOS component comprises identifying one of a primary partition characteristic and a secondary partition characteristic associated with the BIOS component.

4. A method as defined in claim 1 , wherein determining the storing characteristic associated with the BIOS component comprises determining the storing characteristic associated with one of a code area and a data area.

5. A method as defined in claim 1 , wherein determining boundaries of the BIOS component within the non-volatile memory comprises adjusting one of a top portion, a mid-point portion, and a bottom portion of a flash memory with at least one offset.

6. A method as defined in claim 1 , wherein determining boundaries of the BIOS component within the non-volatile memory comprises subtracting at least one offset from a top portion of a flash memory in response to detecting a primary partition identifier associated with the BIOS component.

7. A method as defined in claim 1 , wherein determining boundaries of the BIOS component within the non-volatile memory comprises subtracting at least one offset from a mid-point portion of a flash memory in response to detecting a secondary partition identifier associated with the BIOS component.

8. A machine readable medium storing instructions, which when executed, cause a machine to:

determine a storing characteristic associated with a BIOS component stored in a non-volatile memory;

determine whether the BIOS component is a shared BIOS component or a non-shared BIOS component;

determine boundaries of the BIOS component based on the storing characteristic associated with the BIOS component and whether the BIOS component is a shared BIOS component or a non-shared BIOS component; and

update the BIOS component within the boundaries.

9. A machine readable medium as defined in claim 8 , wherein the instructions cause the machine to determine the storing characteristic associated with the BIOS component by querying for a partition identifier associated with a BIOS component stored in a flash memory.

10. A machine readable medium as defined in claim 8 , wherein the instructions cause the machine to determine the storing characteristic associated with the BIOS component by identifying one of a primary partition characteristic and a secondary partition characteristic associated with the BIOS component.

11. A machine readable medium as defined in claim 8 , wherein the instructions cause the machine to determine the storing characteristic associated with the BIOS component by determining the storing characteristic associated with one of a code area and a data area.

12. A machine readable medium as defined in claim 8 , wherein the instructions cause the machine to determine boundaries of the BIOS component within the non-volatile memory by adjusting one of a top portion, a mid-point portion, and a bottom portion of a flash memory with at least one offset.

13. A machine readable medium as defined in claim 8 , wherein the instructions cause the machine to determine boundaries of the BIOS component within the non-volatile memory comprises subtracting at least one offset from a top portion of a flash memory in response to detecting a primary partition identifier associated with the BIOS component.

14. A machine readable medium as defined in claim 8 , wherein the instructions cause the machine to determine boundaries of the BIOS component within the non-volatile memory by subtracting at least one offset from a mid-point portion of a flash memory in response to detecting a secondary partition identifier associated with the BIOS component.

15. A machine readable medium as defined in claim 8 , wherein the machine readable medium comprises one of a programmable gate array, application specific integrated circuit, erasable programmable read only memory, read only memory, random access memory, magnetic media, and optical media.

16. A processor system comprising:

a data structure; and

a processor operatively coupled to the data structure, the processor being programmed to determine a storing characteristic associated with a BIOS component stored in the data structure, to determine whether the BIOS component is a shared BIOS component or a non-shared BIOS component, to determine boundaries of the BIOS component based on the storing characteristic and the operating characteristic associated with the BIOS component and whether the BIOS component is a shared BIOS component or a non-shared BIOS component, and update the BIOS component within the boundaries.

17. An apparatus as defined in claim 16 , wherein the storing characteristic comprises one of a primary partition characteristic and a secondary partition characteristic.

18. An apparatus as defined in claim 16 , wherein the BIOS component comprises one of a code area and a data area.

19. An apparatus as defined in claim 16 , wherein the boundaries of the BIOS component comprise at least one offset adjusted from one of a top portion, a mid-point portion, and a bottom portion of a flash memory.

20. An apparatus as defined in claim 16 , wherein the processor is programmed to subtract at least one offset from a top portion of a flash memory in response to detecting a primary partition characteristic associated with the BIOS component.

21. An apparatus as defined in claim 16 , wherein the processor is programmed to subtract at least one offset from a mid-point portion of a flash memory in response to detecting a secondary partition characteristic associated with the BIOS component.

22. A processor system comprising:

a flash memory; and

a processor operatively coupled to the flash memory, the processor being programmed to determine a storing characteristic associated with a BIOS component stored in the flash memory, to determine whether the BIOS component is a shared BIOS component or a non-shared BIOS component, to determine boundaries of the BIOS component based on the storing characteristic associated with the BIOS component and whether the BIOS component is a shared BIOS component or a non-shared BIOS component, and update the BIOS component within the boundaries.

23. An apparatus as defined in claim 22 , wherein the storing characteristic comprises one of a primary partition characteristic and a secondary partition characteristic.

24. An apparatus as defined in claim 22 , wherein the BIOS component comprises one of a code area and a data area.

25. An apparatus as defined in claim 22 , wherein the boundaries of the BIOS component comprise at least one offset adjusted from one of a top portion, a mid-point portion, and a bottom portion of a flash memory.

26. An apparatus as defined in claim 22 , wherein the processor is programmed to subtract at least one offset to a top portion of a flash memory in response to detecting a primary partition characteristic associated with the BIOS component.

27. An apparatus as defined in claim 22 , wherein the processor is programmed to subtract at least one offset to a mid-point portion of a flash memory in response to detecting a secondary partition characteristic associated with the BIOS component.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2003
From: BULUSU, MALLIK; ZIMMER, VINCENT; HIRAY, SANDIP
To: INTEL CORPORATION
Reel/Frame 014160/0656 →
Continuity (1)
Related Publication 20040236936A1 · Nov 25, 2004