Interlocking via for package via integrity
View Patent ↗A method of forming an interconnection structure in a microelectronic package, and an interconnection structure of a microelectronic package formed according to the method. The method includes: providing a combination including a first conductive layer and a dielectric layer fixed to the conductive layer; providing a hole through the dielectric layer extending from a surface of the dielectric layer to the first conductive layer; providing a recess in the first conductive layer and in communication with the hole to provide an interlocking volume under the dielectric layer; providing a conductive material in the hole and in the recess to form a package via having an interlocking section in the interlocking volume of the recess; and providing a conductive material on the dielectric layer to form a second conductive layer adapted to be in electrical contact with the first conductive layer through the package via.
1. An interconnection structure of a microelectronic package comprising:
a first conductive layer;
a second conductive layer disposed at a distance with respect to the first conductive layer;
a third conductive layer disposed at a distance with respect to the second conductive layer;
a dielectric material comprising;
a first dielectric material portion disposed between the first conductive layer and the second conductive layer;
a second dielectric material portion disposed between the second conductive layer and the third conductive layer; and
a pair of package vias comprising:
a first package via comprising a first conductive material extending through a first via hole through the first dielectric material portion from the second conductive layer to the first conductive layer, the first package via defining a first interlocking section wider than the first via hole and extending into the first conductive layer and under the first dielectric material portion; and
a second package via comprising a second conductive material extending through a second via hole through the second dielectric material portion from the third conductive layer to the second conductive layer, the second package via defining a second interlocking section wider than the second via hole and extending into the second conductive layer and under the second dielectric material portion.
2. The interconnection structure of claim 1 , wherein at least one of the first package via and the second package via comprises copper.
3. The interconnection structure of claim 1 , wherein at least one of the first interlocking section and the second interlocking section is one of anchor-shaped end T shaped.
4. The interconnection structure of claim 1 , wherein at least one of the first interlocking package via and the second package via is one of a blind via and a through via.
5. The interconnection structure of claim 1 , wherein at least one of the first conductive material and the second conductive material comprises;
a conductive seed layer adjacent a corresponding one of the first dielectric material portion and the second dielectric portion and adjacent a corresponding one of the first conductive layer and the second conductive layer, and
a bulk conductive material on the seed layer to form an associated one of the first package via and the second package via.
6. The interconnection structure of claim 1 , wherein the first package via and the second package via are one of stacked and staggered with respect to one another.
7. The interconnection structure of claim 1 , wherein the first and second package vias comprise copper.
8. A system comprising:
an electronic assembly including a microelectronic package, the package having an interconnection structure therein comprising:
a first conductive layer;
a second conductive layer disposed at a distance with respect to the first conductive layer;
a third conductive layer disposed at a distance with respect to the second conductive layer;
a dielectric material comprising;
a first dielectric material portion disposed between the first conductive layer and the second conductive layer;
a second dielectric material portion disposed between the second conductive layer and the third conductive layer and a pair of package vias comprising;
a first package via comprising a first conductive material extending from the second conductive layer through the first dielectric material portion to the first conductive layer, the first package via defining a first interlocking section extending into the first conductive layer and under the first dielectric material portion; and
a second package via comprising a second conductive material extending from the third conductive layer through the second dielectric material portion to the second conductive layer, the second package defining a second interlocking section extending into the second conductive layer and under the second dielectric material portion; and
a first package via comprising a first conductive material extending through a first via hole through the first dielectric material portion from the second conductive layer to the first conductive layer, the first package via defining a first interlocking section wider than the first via hole and extending into the first conductive layer and under the first dielectric material portion; and
a second package via comprising a second conductive material extending through a second via hole through the second dielectric material portion from the third conductive layer to the second conductive layer, the second package via defining a second interlocking section wider than the second via hole and extending into the second conductive layer and under the second dielectric material portion;
a graphics processor coupled to the electronic assembly.
9. The system of claim 8 , wherein at least one of the first package via and the second package via comprises copper.
10. The system of claim 8 , wherein at least one of the first conductive material and the second conductive material comprises:
a conductive seed layer adjacent a corresponding one of the first dielectric material portion and the second dielectric portion and adjacent a corresponding one of the first conductive layer and the second conductive layer, and
a bulk conductive material on the seed layer to form an associated one of the first package via end the second package via.
11. The system of claim 8 , wherein the first package via and the second package via are one of stacked and staggered with respect to one another.