Method for synchronizing processors in a multiprocessor system
The high-speed barrier synchronization is completed among multiprocessors by saving overhead for parallel process without addition of a particular hardware mechanism. That is, the barrier synchronization process is performed by allocating the synchronization flag area, on the shared memory, indicating the synchronization point where the execution of each processor for completing the barrier synchronization is completed, updating the synchronization flag area with the software in accordance with the executing condition, and comparing, with each processor, the synchronization flag area of the other processors which takes part in the barrier synchronization.
1. A synchronizing method of multiprocessor system for barrier synchronization to execute parallel processes of program in a plurality of processors, comprising the steps of:
providing, in said multiprocessor system, a shared memory area which is used in common by each processor;
allocating individual memory areas for each processor in said shared memory area;
providing, within said memory area, a counter for storing an execution count by each processor which has executed the process for a part to complete the barrier synchronization in said program; and
executing subsequent programs to be executed by each processor after writing, with addition, the value of said counter of the individual memory area allocated to own processor when the part to complete the barrier synchronization in the program is executed and after determining that the identical value or more larger value is written to all memory areas allocated to the other processors.
2. A synchronization method of multiprocessor system for barrier synchronization to execute parallel processes of the program in a plurality of processors, comprising the steps of:
providing, in said multiprocessor system, a shared memory area which is used in common by each processor;
allocating individual memory area for each processor in said shared memory area;
providing, in said memory area, a counter for storing a value corresponding to an execution count by each processor which has executed the process for a part to complete the barrier synchronization in the program;
obtaining a value corresponding to the execution count from a sequence for determining a value corresponding to the execution count by each processor when the part to complete the barrier synchronization in the program is executed, and writing said value to the counter in the individual memory areas allocated to own processor; and
executing subsequent programs after determining that the identical value is written into all memory areas allocated to the other processors or the value corresponding to the count obtained by adding 1 to said execution count is written in said sequence.
3. The synchronization method of multiprocessor system according to claim 1 or 2 , wherein said processors comprise cache memories, and an interval of the addresses on the memory of memory area to be allocated individually to each processor is set equal to or larger than a processing unit in a management for maintaining coherence among the cache memories loaded to said processors.
4. The synchronization method of multiprocessor system according to claim 1 or 2 , wherein said processors comprise cache memories and a mechanism for maintaining coherence among the cache memories, a cache memory for individual memory area to be allocated for each processor is set, and the barrier synchronization is performed utilizing said cache memory.
5. The synchronization method of multiprocessor system according to claim 2 , wherein a sequence for determining a unique value in accordance with the execution count of the part to complete the barrier synchronization in said program repeats the identical sequence for a constant execution count.
6. The synchronization method of multiprocessor according to claim 5 , wherein said sequence includes at least three values including a first value indicating that the previous barrier synchronization has been completed and the present barrier synchronization is being executed, a second value indicating that the present barrier synchronization has been completed, and a third value indicating that the next barrier synchronization has been completed.