Reducing plasma ignition pressure

1. In a plasma processing system having a plasma processing chamber and an electrostatic chuck coupled to a bias compensation circuit, a method for processing a semiconductor substrate, comprising:

igniting a plasma in a plasma ignition step, said plasma ignition step being performed while a first bias compensation voltage provided by said bias compensation circuit to said chuck is substantially zero and while a first chamber pressure within said plasma processing chamber is below about 90 mTorr;

after said plasma is ignited, processing said substrate in a substrate-processing step, said substrate-processing step employing a second bias compensation voltage provided by said bias compensation circuit that is higher than said first bias compensation voltage and a second chamber pressure substantially equal to said first chamber pressure.

2. The method of claim 1 wherein said first bias compensation voltage is employed only long enough to prepare said plasma for said substrate-processing step.

3. The method of claim 2 wherein a duration of said plasma ignition step is below about 10 seconds.

4. The method of claim 2 wherein a duration of said plasma ignition step is below about 5 seconds.

5. The method of claim 1 wherein said igniting said plasma is performed while said first bias compensation voltage is zero.

6. The method of claim 1 wherein said igniting said plasma is performed while said first chamber pressure is between about 40 mTorr and about 90 mTorr.

7. The method of claim 1 wherein said igniting said plasma is performed while said first chamber pressure is between about 50 mTorr and about 80 mTorr.

8. The method of claim 1 wherein said igniting said plasma is performed while said first chamber pressure is between about 60 mTorr and about 60 mTorr.

9. The method of claim 1 wherein said igniting said plasma is performed while said first chamber pressure is below about 60 mTorr.

10. The method of claim 1 wherein said igniting said plasma is performed while said first chamber pressure is below about 50 mTorr.

11. The method of claim 1 wherein said plasma processing system represents an inductively-coupled plasma processing system.

12. The method of claim 1 wherein said plasma processing system represents a capacitively-coupled plasma processing system.

13. The method of claim 1 wherein said plasma processing system represents an ECR plasma processing system.

14. The method of claim 1 wherein said electrostatic chuck is a multi-polar electrostatic chuck.

15. The method of claim 1 wherein said electrostatic chuck is a bi-polar electrostatic chuck.

16. The method of claim 1 wherein said electrostatic chuck is a mono-polar electrostatic chuck.

17. The method of claim 1 wherein said processing represents an etch application.

18. The method of claim 1 wherein said substrate represents a semiconductor wafer for producing integrated circuit.

19. The method of claim 1 wherein said substrate represents a flat panel substrate for producing at least one flat panel display product.

20. The method of claim 1 wherein said substrate represents a nano-machine substrate for producing nano-machines.

21. In a plasma processing system having a plasma processing chamber and an electrostatic chuck coupled to a bias compensation circuit, a method for processing a substrate, comprising:

igniting a plasma while a first bias compensation voltage provided by said bias compensation circuit to said chuck is substantially zero;

after said plasma is ignited, processing said substrate using a second bias compensation voltage higher than said first bias compensation voltage.

22. The method of claim 21 wherein said first bias compensation voltage is employed only long enough to ignite said plasma.

23. The method of claim 21 wherein said igniting said plasma is performed while said first bias compensation voltage is zero.

24. The method of claim 21 wherein said igniting said plasma is performed while a chamber pressure within said plasma processing chamber is between about 40 mTorr and about 90 mTorr.

25. The method of claim 21 wherein said igniting said plasma is performed while a chamber pressure within said plasma processing chamber is between about 50 mTorr and about 80 mTorr.

26. The method of claim 21 wherein said igniting said plasma is performed while a chamber pressure within said plasma processing chamber is between about 60 mTorr and about 60 mTorr.

27. The method of claim 21 wherein said igniting said plasma is performed while a chamber pressure within said plasma processing chamber is below about 60 mTorr.

28. The method of claim 21 wherein said igniting said plasma is performed while a chamber pressure within said plasma processing chamber is below about 50 mTorr.

29. The method of claim 21 wherein said processing said substrate is performed at substantially the same chamber pressure as a chamber pressure that exists during said igniting said plasma.

30. The method of claim 21 wherein said plasma processing system represents an inductively-coupled plasma processing system.

31. The method of claim 21 wherein said plasma processing system represents a capacitively-coupled plasma processing system.

32. The method of claim 21 wherein said plasma processing system represents an ECR plasma processing system.

33. The method of claim 21 wherein said electrostatic chuck is a multi-pole electrostatic chuck.

34. The method of claim 21 wherein said electrostatic chuck is a bi-polar electrostatic chuck.

35. The method of claim 21 wherein said electrostatic chuck is a mono-polar electrostatic chuck.

36. The method of claim 21 wherein said processing represents an etch application.

37. The method of claim 21 wherein said substrate represents a semiconductor wafer for producing integrated circuit.

38. The method of claim 21 wherein said substrate represents a flat panel substrate for producing at least one flat panel display product.

39. The method of claim 21 wherein said substrate represents a nano-machine substrate for producing nano-machines.