IP Library Granted Patent US 7,199,053
Granted Patent B2
US 7,199,053 · App. 10/876,686 · Granted Apr 3, 2007

Method for detecting end-point of chemical mechanical polishing process

Assignee: Hynix Semiconductor Inc.
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Quick Facts
Patent No.
US 7,199,053
App. No.
10/876,686
Granted
Apr 3, 2007
Kind
B2
Abstract

Disclosed is a method for detecting an end-point of a CMP process of a semiconductor device. More specifically, when all polishing processes are performed using a nitride film as a polishing barrier film, a buffer layer including nitrogen is formed on the nitride film and a polishing process is performed. Then, the concentration of NO from ammonia gas generated from the buffer layer is detected so that the nitride film may be polished to a desired target without damage of the nitride film. As a result, an end-point can be set.

Claims (25)

1. A method for detecting an end-point of a CMP process of a semiconductor device, comprising the steps of:

sequentially forming a polysilicon film, a conductive layer, a hard mask nitride film on a semiconductor substrate;

forming a buffer layer containing nitrogen on the hard mask nitride film;

selectively etching the buffer layer, the hard mask nitride film, the conductive layer and the polysilicon film to form a gate line including a stacked structure of a polysilicon film pattern, a conductive layer pattern, a hard mask nitride film pattern and a buffer layer pattern;

forming a spacer at a sidewall of the gate line;

forming an interlayer insulating film on the semiconductor substrate including the gate line and the spacer; and

subjecting the insulating film and the buffer layer of a CMP process using the hard mask nitride film pattern as an etching barrier film,

wherein a concentration of NO gas generated upon exposure of the buffer layer in the CMP process is measured so as to detect an end-point of the CMP process.

2. The method according to claim 1 , wherein the buffer layer comprises a SiON or a Si-rich SiON film.

3. The method according to claim 1 , wherein a thickness of the buffer layer ranges from 200 to 1000 Å.

4. The method according to claim 1 , wherein the conductive layer comprises a material selected from a group consisting of a doped silicon, polysilicon, tungsten, tungsten nitride, tungsten suicide and titanium suicide.

5. The method according to claim 1 , wherein the selective etching process comprises a plasma etching process using a chlorine gas as a source.

6. The method according to claim 1 , wherein the spacer is formed via a LP-CVD (low pressure chemical vapor deposition) method using TEOS (Tetraethoxysilicate glass) film or silane (SiH 4 )-base oxide film.

7. The method according to claim 1 , wherein the interlayer insulating film is selected from a group consisting of BPSG (boron phosphosilicate glass) film, a PSG (phosphosilicate glass) film, a FSG (fluorosilicate glass) film, a PE-TEOS (plasma enhanced tetraethoxysilicate glass) oxide film, a PE-SiH 4 (plasma enhanced-silane) film, a APL (advanced planarization layer) oxide film, a ALD (atomic layer deposition) oxide film and a HDP (high density plasma) oxide film.

8. The method according to claim 7 , wherein the HDP oxide film is formed from a source selected from a group consisting of TEOS,SiH 4 , SiH n (CH 3)m (0≦n≦4, 0≦m≦4), N 2 N 2 O, NH 3 , O 2 , O 3 , Ar, He and NF 3 .

9. The method according to claim 7 , further comprising subjecting the HDP oxide film to a thermal process performed in an atmosphere of a gas selected from a group consisting of H 2 , O 2 , N 2 , O 3 , N 2 O and H 2 + O 2 .

10. The method according to claim 7 , further comprising subjecting the HDP oxide film to a rapid thermal processing (RTP) performed at a temperature ranging from 600 to 1500° C.

11. The method according to claim 1 , wherein the CMP process comprises:

polishing the interlayer insulating film using a first slurry until a remaining portion of the interlayer insulating film has at a thickness ranging from 300 to 800 Å; and

polishing the remaining portion of the interlayer insulating film and the buffer layer using a second slurry to expose the hard mask nitride film pattern.

12. The method according to claim 11 , wherein the slurry for oxide film comprises 0.5.about. 10 wt % of an abrasive selected from a group consisting of colloidal or fumed SiO 2 having a grain size ranging from 50 to 500 nm, Al 2 O 3 , CeO 2 and ZrO 2 .

13. The method according to claim 11 , wherein the first slurry has a polishing selectivity ratio of an oxide film to nitride film ranging from 1:1.about. 10:1.

14. The method according to claim 11 , wherein the second slurry comprises a slurry for oxide film having a pH ranging from 3 to 8 containing CeO 2 abrasive.

15. The method according to claim 11 , wherein the second slurry has a polishing selectivity ratio of an oxide film to nitride film ranging from 10:1 to about 150:1.

16. The method according to claim 1 , wherein the CMP process is performed at a polishing pressure ranging from 1 to 10 psi and at a polishing table speed ranging from 10 to 100 rpm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2004
From: JUNG, JONG GOO
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 015526/0686 →
Priority Claims (1)
KR 10-2003-0096266 · Dec 24, 2003 · national
Continuity (1)
Related Publication 20050142878A1 · Jun 30, 2005