Phase locked loop system capable of deskewing

1. A system comprising:

a phase lock loop component to output a first signal based on a reference clock signal and a feedback clock signal;

a clock distribution network to distribute a clock signal based on the first signal output from the phase lock loop component, wherein the clock distribution network is outside a feedback path of the phase lock loop component; and

a delay lock loop component to adjust the clock signal distributed by the clock distribution network, wherein the delay lock loop component comprises a phase detector and a variable delay circuit, the phase detector to output an adjustment signal to the variable delay circuit, and the phase detector is to compare a signal output from the variable delay circuit with the clock signal distributed by the clock distribution network to determine the adjustment signal;

wherein the variable delay circuit is provided outside a feedback path of the phase lock loop component.

2. The system of claim 1 , further comprising a divider circuit to lock the phase lock loop component.

3. The system of claim 1 , wherein the delay lock loop component is to deskew the clock signal distributed by the clock distribution network up to a maximum of one period of said clock signal.

4. A system comprising:

a phase lock loop component to output a first clock signal;

a clock distribution network to provide a second clock signal based on the first clock signal output from the phase lock loop component, wherein the clock distribution network is outside a feedback path of the phase lock loop component; and

a delay lock loop component to adjust a timing of the second clock signal, wherein the delay lock loop component comprises a phase detector and a variable delay circuit, the phase detector to output an adjustment signal to the variable delay circuit;

wherein the variable delay circuit is provided outside the feedback path of the phase lock loop component.

5. The system of claim 4 , further comprising a divider circuit to lock the phase lock loop component.

6. The system of claim 4 , wherein the delay lock loop component is to adjust the timing of the second clock signal up to a maximum of one period of said second clock signal.

7. A system comprising:

a phase lock loop component to output a first signal based on a reference clock signal and a feedback clock signal;

a clock distribution network to distribute a clock signal based on the first signal output from the phase lock loop component, wherein the clock distribution network is outside a feedback path of the phase lock loop component; and

a delay lock loop component to adjust the clock signal distributed by the clock distribution network, wherein the delay lock loop component comprises a phase detector and a variable delay circuit, the phase detector to output an adjustment signal to the variable delay circuit;

wherein the delay lock loop component is to deskew the clock signal distributed by the clock distribution network up to a maximum of one period of said clock signal.

8. A system comprising:

a phase lock loop component to output a first signal based on a reference clock signal and a feedback clock signal;

a clock distribution network to distribute a clock signal based on the first signal output from the phase lock loop component, wherein the clock distribution network is outside a feedback path of the phase lock loop component; and

a delay lock loop component to adjust the clock signal distributed by the clock distribution network, wherein the delay lock loop component comprises a phase detector and a variable delay circuit, the phase detector to output an adjustment signal to the variable delay circuit, wherein the variable delay circuit is to output the reference clock signal to the phase lock loop component.

9. A system comprising:

a phase lock loop component to output a first signal based on a reference clock signal and a feedback clock signal;

a clock distribution network to distribute a clock signal based on the first signal output from the phase lock loop component, wherein the clock distribution network is outside a feedback path of the phase lock loop component; and

a delay lock loop component to adjust the clock signal distributed by the clock distribution network, wherein a variable delay circuit is to receive a second signal and output the reference clock signal to the phase lock loop component, the variable delay circuit to adjust the reference clock signal based on an adjustment signal output from the phase detector.

10. The system of claim 9 , wherein the adjustment signal is based on the clock signal distributed by the clock distribution network and the second signal.

11. A system comprising:

a phase lock loop component to output a first clock signal;

a clock distribution network to provide a second clock signal based on the first clock signal output from the phase lock loop component, wherein the clock distribution network is outside a feedback path of the phase lock loop component; and

a delay lock loop component to adjust a timing of the second clock signal, wherein the delay lock loop component comprises a phase detector and a variable delay circuit, the phase detector to output an adjustment signal to the variable delay circuit, and wherein the variable delay circuit is to align the second clock signal with a feedback clock signal of the phase lock loop component;

wherein the delay lock loop component is to deskew the second clock signal distributed by the clock distribution network up to a maximum of one period of said clock signal.

12. A system comprising:

a phase lock loop component to output a first clock signal;

a clock distribution network to provide a second clock signal based on the first clock signal output from the phase lock loop component, wherein the clock distribution network is outside a feedback path of the phase lock loop component; and

a delay lock loop component to adjust a timing of the second clock signal, wherein the delay lock loop component comprises a phase detector and a variable delay circuit, the phase detector to output an adjustment signal to the variable delay circuit, and wherein the variable delay circuit is to align the second clock signal with a feedback clock signal of the phase lock loop component, wherein the variable delay circuit is to receive a third signal and output a reference clock signal to the phase lock loop component, the variable delay circuit to adjust the reference clock signal based on the adjustment signal output from the phase detector.

13. The system of claim 12 , wherein the adjustment signal is based on the second clock signal.

14. A system comprising:

a phase lock loop component to output a first signal based on a reference clock signal and a feedback clock signal;

a clock distribution network to distribute a clock signal based on the first signal output from the phase lock loop component, wherein the clock distribution network is outside a feedback path of the phase lock loop component; and

a delay lock loop component to adjust the clock signal distributed by the clock distribution network, wherein the delay lock loop component comprises a phase detector and a variable delay circuit, the phase detector to output an adjustment signal to the variable delay circuit, and the phase detector is to compare a signal output from the variable delay circuit with the clock signal distributed by the clock distribution network to determine the adjustment signal;

wherein the delay lock loop component is to deskew the clock signal distributed by the clock distribution network up to a maximum of one period of said clock signal.

15. The system of claim 1 , wherein the variable delay circuit is provided outside the feedback path of the phase lock loop component.