Duty cycle correction circuits suitable for use in delay-locked loops and methods of correcting duty cycles of periodic signals
Delay-locked loop integrated circuits include a duty cycle correction circuit. This duty cycle correction circuit generates at least one output clock signal having a substantially uniform duty cycle in response to at least one input clock signal having a non-uniform duty cycle. The duty cycle correction circuit is also responsive to a standby control signal that synchronizes timing of power-saving duty cycle update operations within the duty cycle correction circuit. These update operations reset the set point of the correction circuit.
1. An integrated circuit device, comprising:
a duty cycle correction circuit configured to generate a complementary pair of output clock signals having substantially uniform duty cycles in response to a complementary pair of input clock signals having non-uniform duty cycles and a standby control signal that synchronizes timing of power-saving duty cycle update operations within said duty cycle correction circuit, said duty cycle correction circuit comprising:
a duty cycle correction amplifier configured to generate the complementary pair of output clock signals in response to the complementary pair of input clock signals;
a duty cycle detector configured to generate a complementary pair of pump output signals in response to the complementary pair of output clock signals;
a comparator configured to generate a comparator output signal in response to the complementary pair of pump output signals;
a counter configured to generate a digital output signal in response to the comparator output signal and the standby control signal; and
a digital-to-analog converter configured to generate a complementary pair of analog output signals in response to the digital output signal.
2. The device of claim 1 , wherein said duty cycle correction circuit is responsive to the complementary pair of pump output signals and the complementary pair of analog output signals.
3. The device of claim 2 , further comprising a delay-locked loop configured to generate at least one of the complementary pair of input clock signals in response to an external clock signal.
4. An integrated circuit device, comprising:
a duty cycle correction circuit configured to generate a complementary pair of output clock signals having substantially uniform duty cycles in response to a complementary pair of input clock signals having non-uniform duty cycles and support a power-saving mode of operation that temporarily stalls periodic switching of the complementary pair of output clock signals while a set point of the duty cycle correction circuit is updated, said duty cycle correction circuit comprising:
a duty cycle correction amplifier configured to generate the complementary pair of output clock signals in response to the complementary pair of input clock signals;
a duty cycle detector configured to generate a complementary pair of pump output signals in response to the complementary pair of output clock signals;
a comparator configured to generate a comparator output signal in response to the complementary pair of pump output signals;
a counter configured to generate a digital output signal in response to the comparator output signal and a standby control signal; and
a digital-to-analog converter configured to generate a complementary pair of analog output signals in response to the digital output signal.
5. The device of claim 4 , wherein said duty cycle correction circuit is responsive to the complementary pair of pump output signals and the complementary pair of analog output signals.